SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
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68af3f2491
commit
c2432a42fe
52
hw/sh7750.c
52
hw/sh7750.c
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@ -42,8 +42,12 @@ typedef struct SH7750State {
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uint32_t periph_freq;
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uint32_t periph_freq;
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/* SDRAM controller */
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/* SDRAM controller */
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uint32_t bcr1;
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uint32_t bcr1;
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uint32_t bcr2;
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uint16_t bcr2;
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uint16_t bcr3;
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uint32_t bcr4;
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uint16_t rfcr;
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uint16_t rfcr;
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/* PCMCIA controller */
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uint16_t pcr;
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/* IO ports */
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/* IO ports */
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uint16_t gpioic;
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uint16_t gpioic;
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uint32_t pctra;
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uint32_t pctra;
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@ -66,7 +70,10 @@ typedef struct SH7750State {
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struct intc_desc intc;
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struct intc_desc intc;
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} SH7750State;
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} SH7750State;
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static int inline has_bcr3_and_bcr4(SH7750State * s)
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{
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return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
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}
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/**********************************************************************
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/**********************************************************************
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I/O ports
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I/O ports
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**********************************************************************/
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**********************************************************************/
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@ -211,8 +218,14 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
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switch (addr) {
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switch (addr) {
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case SH7750_BCR2_A7:
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case SH7750_BCR2_A7:
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return s->bcr2;
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return s->bcr2;
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case SH7750_BCR3_A7:
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if(!has_bcr3_and_bcr4(s))
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error_access("word read", addr);
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return s->bcr3;
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case SH7750_FRQCR_A7:
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case SH7750_FRQCR_A7:
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return 0;
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return 0;
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case SH7750_PCR_A7:
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return s->pcr;
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case SH7750_RFCR_A7:
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case SH7750_RFCR_A7:
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fprintf(stderr,
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fprintf(stderr,
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"Read access to refresh count register, incrementing\n");
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"Read access to refresh count register, incrementing\n");
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@ -221,6 +234,11 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
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return porta_lines(s);
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return porta_lines(s);
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case SH7750_PDTRB_A7:
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case SH7750_PDTRB_A7:
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return portb_lines(s);
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return portb_lines(s);
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case SH7750_RTCOR_A7:
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case SH7750_RTCNT_A7:
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case SH7750_RTCSR_A7:
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ignore_access("word read", addr);
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return 0;
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default:
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default:
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error_access("word read", addr);
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error_access("word read", addr);
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assert(0);
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assert(0);
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@ -235,6 +253,9 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
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case SH7750_BCR1_A7:
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case SH7750_BCR1_A7:
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return s->bcr1;
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return s->bcr1;
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case SH7750_BCR4_A7:
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case SH7750_BCR4_A7:
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if(!has_bcr3_and_bcr4(s))
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error_access("long read", addr);
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return s->bcr4;
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case SH7750_WCR1_A7:
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case SH7750_WCR1_A7:
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case SH7750_WCR2_A7:
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case SH7750_WCR2_A7:
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case SH7750_WCR3_A7:
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case SH7750_WCR3_A7:
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@ -271,19 +292,19 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
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}
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}
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}
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}
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#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
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&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
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static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
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static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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uint32_t mem_value)
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{
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{
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switch (addr) {
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/* PRECHARGE ? XXXXX */
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if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
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case SH7750_PRECHARGE0_A7:
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case SH7750_PRECHARGE1_A7:
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ignore_access("byte write", addr);
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ignore_access("byte write", addr);
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return;
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return;
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default:
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error_access("byte write", addr);
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assert(0);
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}
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}
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error_access("byte write", addr);
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assert(0);
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}
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}
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static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
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static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
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@ -298,8 +319,15 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
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s->bcr2 = mem_value;
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s->bcr2 = mem_value;
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return;
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return;
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case SH7750_BCR3_A7:
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case SH7750_BCR3_A7:
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case SH7750_RTCOR_A7:
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if(!has_bcr3_and_bcr4(s))
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error_access("word write", addr);
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s->bcr3 = mem_value;
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return;
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case SH7750_PCR_A7:
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s->pcr = mem_value;
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return;
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case SH7750_RTCNT_A7:
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case SH7750_RTCNT_A7:
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case SH7750_RTCOR_A7:
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case SH7750_RTCSR_A7:
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case SH7750_RTCSR_A7:
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ignore_access("word write", addr);
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ignore_access("word write", addr);
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return;
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return;
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@ -343,6 +371,10 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
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s->bcr1 = mem_value;
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s->bcr1 = mem_value;
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return;
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return;
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case SH7750_BCR4_A7:
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case SH7750_BCR4_A7:
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if(!has_bcr3_and_bcr4(s))
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error_access("long write", addr);
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s->bcr4 = mem_value;
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return;
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case SH7750_WCR1_A7:
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case SH7750_WCR1_A7:
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case SH7750_WCR2_A7:
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case SH7750_WCR2_A7:
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case SH7750_WCR3_A7:
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case SH7750_WCR3_A7:
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@ -80,8 +80,8 @@ static regname_t regnames[] = {
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REGNAME(SH7750_ICR_A7)
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REGNAME(SH7750_ICR_A7)
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REGNAME(SH7750_BCR3_A7)
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REGNAME(SH7750_BCR3_A7)
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REGNAME(SH7750_BCR4_A7)
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REGNAME(SH7750_BCR4_A7)
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REGNAME(SH7750_PRECHARGE0_A7)
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REGNAME(SH7750_SDMR2_A7)
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REGNAME(SH7750_PRECHARGE1_A7) {(uint32_t) - 1, 0}
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REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, 0}
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};
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};
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const char *regname(uint32_t addr)
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const char *regname(uint32_t addr)
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@ -979,6 +979,17 @@
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#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
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#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */
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/* Synchronous DRAM mode registers - SDMR */
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#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */
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#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */
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#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS)
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#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS)
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#define SH7750_SDMR3_REGOFS 0x940000 /* offset */
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#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */
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#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS)
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#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS)
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/*
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/*
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* Direct Memory Access Controller (DMAC)
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* Direct Memory Access Controller (DMAC)
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*/
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*/
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@ -1262,7 +1273,5 @@
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*/
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*/
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#define SH7750_BCR3_A7 0x1f800050
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#define SH7750_BCR3_A7 0x1f800050
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#define SH7750_BCR4_A7 0x1e0a00f0
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#define SH7750_BCR4_A7 0x1e0a00f0
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#define SH7750_PRECHARGE0_A7 0x1f900088
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#define SH7750_PRECHARGE1_A7 0x1f940088
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#endif
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#endif
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@ -95,6 +95,7 @@ typedef struct tlb_t {
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enum sh_features {
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enum sh_features {
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SH_FEATURE_SH4A = 1,
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SH_FEATURE_SH4A = 1,
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SH_FEATURE_BCR3_AND_BCR4 = 2,
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};
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};
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typedef struct CPUSH4State {
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typedef struct CPUSH4State {
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@ -222,12 +222,14 @@ static sh4_def_t sh4_defs[] = {
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.pvr = 0x00050000,
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.pvr = 0x00050000,
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.prr = 0x00000100,
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.prr = 0x00000100,
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.cvr = 0x00110000,
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.cvr = 0x00110000,
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.features = SH_FEATURE_BCR3_AND_BCR4,
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}, {
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}, {
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.name = "SH7751R",
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.name = "SH7751R",
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.id = SH_CPU_SH7751R,
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.id = SH_CPU_SH7751R,
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.pvr = 0x04050005,
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.pvr = 0x04050005,
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.prr = 0x00000113,
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.prr = 0x00000113,
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.cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
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.cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
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.features = SH_FEATURE_BCR3_AND_BCR4,
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}, {
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}, {
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.name = "SH7785",
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.name = "SH7785",
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.id = SH_CPU_SH7785,
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.id = SH_CPU_SH7785,
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