Acer Pica 61 machine, by Herve Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2687 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -425,7 +425,8 @@ VL_OBJS+= grackle_pci.o prep_pci.o unin_pci.o
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CPPFLAGS += -DHAS_AUDIO
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endif
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ifeq ($(TARGET_BASE_ARCH), mips)
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VL_OBJS+= mips_r4k.o mips_malta.o mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o
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VL_OBJS+= mips_r4k.o mips_malta.o mips_pica61.o
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VL_OBJS+= mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o
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VL_OBJS+= ide.o gt64xxx.o pckbd.o ps2.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
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VL_OBJS+= piix_pci.o parallel.o mixeng.o cirrus_vga.o $(SOUND_HW) $(AUDIODRV)
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CPPFLAGS += -DHAS_AUDIO
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@ -0,0 +1,175 @@
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/*
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* QEMU Malta board support
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*
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* Copyright (c) 2007 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BIOS_FILENAME "mips_bios.bin"
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#else
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#define BIOS_FILENAME "mipsel_bios.bin"
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#endif
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#ifdef TARGET_MIPS64
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#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
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#else
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#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
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#endif
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#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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static uint32_t serial_base[MAX_SERIAL_PORTS] = { 0x80006000, 0x80007000 };
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static int serial_irq[MAX_SERIAL_PORTS] = { 8, 9 };
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extern FILE *logfile;
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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}
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static
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void mips_pica61_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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char buf[1024];
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unsigned long bios_offset;
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int bios_size;
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CPUState *env;
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int i;
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mips_def_t *def;
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int available_ram;
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qemu_irq *i8259;
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/* init CPUs */
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if (cpu_model == NULL) {
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#ifdef TARGET_MIPS64
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cpu_model = "R4000";
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#else
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cpu_model = "4KEc";
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#endif
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}
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if (mips_find_by_name(cpu_model, &def) != 0)
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def = NULL;
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env = cpu_init();
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cpu_mips_register(env, def);
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM (limited to 256 MB) */
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if (ram_size < 256 * 1024 * 1024)
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available_ram = ram_size;
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else
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available_ram = 256 * 1024 * 1024;
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cpu_register_physical_memory(0, available_ram, IO_MEM_RAM);
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/* load a BIOS image */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if ((bios_size <= 0) || (bios_size > BIOS_SIZE)) {
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/* fatal */
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fprintf(stderr, "qemu: Error, could not load MIPS bios '%s'\n",
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buf);
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exit(1);
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}
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cpu_register_physical_memory(0x1fc00000,
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BIOS_SIZE, bios_offset | IO_MEM_ROM);
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/* Device map
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*
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* addr 0xe0004000: mc146818
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* addr 0xe0005000 intr 6: ps2 keyboard
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* addr 0xe0005000 intr 7: ps2 mouse
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* addr 0xe0006000 intr 8: ns16550a,
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* addr 0xe0007000 intr 9: ns16550a
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* isa_io_base 0xe2000000 isa_mem_base 0xe3000000
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*/
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/* Init CPU internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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cpu_mips_irqctrl_init();
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/* Register 64 KB of ISA IO space at 0x10000000 */
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isa_mmio_init(0x10000000, 0x00010000);
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isa_mem_base = 0x11000000;
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/* PC style IRQ (i8259/i8254) and DMA (i8257) */
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/* The PIC is attached to the MIPS CPU INT0 pin */
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i8259 = i8259_init(env->irq[2]);
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rtc_mm_init(0x80004070, i8259[14]);
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pit_init(0x40, 0);
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/* Keyboard (i8042) */
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i8042_mm_init(i8259[6], i8259[7], 0x80005060, 0);
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/* IDE controller */
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for(i = 0; i < 2; i++)
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isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
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bs_table[2 * i], bs_table[2 * i + 1]);
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/* Network controller */
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/* FIXME: missing NS SONIC DP83932 */
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/* SCSI adapter */
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/* FIXME: missing NCR 53C94 */
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/* ISA devices (floppy, serial, parallel) */
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fdctrl_init(i8259[1], 1, 1, 0x80003000, fd_table);
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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serial_mm_init(serial_base[i], 0, i8259[serial_irq[i]], serial_hds[i], 1);
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}
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}
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for (i = 0; i < MAX_PARALLEL_PORTS; i++) {
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if (parallel_hds[i]) {
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/* FIXME: memory mapped! parallel_init(0x80008000, i8259[17], parallel_hds[i]); */
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}
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}
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/* Sound card */
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/* FIXME: missing Jazz sound, IRQ 18 */
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/* LED indicator */
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/* FIXME: missing LED indicator */
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/* NVRAM */
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ds1225y_init(0x80009000, "nvram");
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/* Video card */
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//isa_vga_init(ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
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}
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QEMUMachine mips_pica61_machine = {
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"pica61",
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"Acer Pica 61",
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mips_pica61_init,
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};
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1
vl.c
1
vl.c
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@ -6697,6 +6697,7 @@ void register_machines(void)
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#elif defined(TARGET_MIPS)
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qemu_register_machine(&mips_machine);
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qemu_register_machine(&mips_malta_machine);
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qemu_register_machine(&mips_pica61_machine);
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#elif defined(TARGET_SPARC)
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#ifdef TARGET_SPARC64
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qemu_register_machine(&sun4u_machine);
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5
vl.h
5
vl.h
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@ -1136,9 +1136,12 @@ extern QEMUMachine mips_machine;
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/* mips_malta.c */
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extern QEMUMachine mips_malta_machine;
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/* mips_int */
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/* mips_int.c */
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extern void cpu_mips_irq_init_cpu(CPUState *env);
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/* mips_pica61.c */
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extern QEMUMachine mips_pica61_machine;
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/* mips_timer.c */
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extern void cpu_mips_clock_init(CPUState *);
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extern void cpu_mips_irqctrl_init (void);
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