Initial support for the ChipCity CC32RS512 smart card
The CC32RS512 is a Smart Card SoC, based on an SC100 ARM core, 18kByte RAM and 512kByte FLASH. It contains a number of integrated peripherals such as the ISO7816 Slave Controller, AES,DES, etc. This emulator is just emulating very basic behavior at this point.
This commit is contained in:
parent
2aeabc0817
commit
a4fb8f496a
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@ -374,6 +374,7 @@ obj-arm-y += vexpress.o
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obj-arm-y += strongarm.o
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obj-arm-y += collie.o
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obj-arm-y += pl041.o lm4549.o
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obj-arm-y += cc32rs512.o cc32_iso_slave.o
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obj-arm-$(CONFIG_FDT) += device_tree.o
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obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
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@ -0,0 +1,301 @@
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/*
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* ChipCity CC32RS512 ISO7816 Slave Controller emulation
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*
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* Copyright (C) 2012 Harald Welte <laforge@gnumonks.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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#include "qemu-char.h"
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#include "qemu-error.h"
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enum iso_slave_reg {
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ISOCON = 0x00,
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ISOCON1 = 0x04,
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ISOCON2 = 0x08,
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ISOSTS = 0x0c,
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ISOBRC = 0x10,
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ISOBUF = 0x14,
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ISODIO = 0x18,
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ISOMSK = 0x1c,
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ISODMACON = 0x30,
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ISODMASTS = 0x34,
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ISODMABFAD = 0x38,
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ISODMABFLEN = 0x3c,
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ISODMABFPT = 0x40,
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ISODMAMSK = 0x44,
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ISOTCON = 0x50,
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ISOTDAT = 0x54,
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ISOTRLD = 0x58,
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ISOTMSK = 0x5c,
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ISONULL = 0x60,
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};
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#define ISOCON_TR (1 << 5)
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#define ISOCON_TACT (1 << 4)
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#define ISOSTS_TBE (1 << 0)
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#define ISOSTS_RBF (1 << 1)
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#define ISOSTS_PE (1 << 2)
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#define ISOSTS_OE (1 << 3)
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#define NUM_REGS 25
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struct CC32IsoSlaveState {
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SysBusDevice busdev;
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MemoryRegion iomem;
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CharDriverState *chr;
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qemu_irq irq;
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uint32_t regs[NUM_REGS];
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};
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typedef struct CC32IsoSlaveState CC32IsoSlaveState;
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static void iso_slave_update_irq(CC32IsoSlaveState *s)
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{
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unsigned int irq = 0;
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if (s->regs[ISOSTS>>2] & s->regs[ISOMSK>>2])
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irq = 1;
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qemu_set_irq(s->irq, irq);
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}
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static uint64_t iso_slave_read(void *opaque, target_phys_addr_t addr, unsigned size)
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{
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CC32IsoSlaveState *s = opaque;
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uint32_t r;
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uint32_t reg_idx = addr >> 2;
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if (addr & 3) {
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error_report("cc32_iso_slave: unaligned read access");
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return 0;
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}
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switch (addr) {
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case ISOBUF:
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r = s->regs[reg_idx];
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s->regs[ISOSTS>>2] &= ~ISOSTS_RBF;
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default:
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r = s->regs[reg_idx];
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break;
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}
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return r;
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}
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static void iso_slave_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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CC32IsoSlaveState *s = opaque;
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uint32_t reg_idx = addr >> 2;
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uint32_t val32 = value;
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uint32_t mask = 0;
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switch (addr) {
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case ISOCON:
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mask = (1 << 5) | (1 << 7);
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break;
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case ISOCON1:
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mask = 0x3F;
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break;
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case ISOCON2:
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mask = (1 << 0) | (1 << 2) | (1 << 7);
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break;
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case ISOSTS:
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if (val32 & (1 << 2)) {
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val32 &= ~(1 << 2);
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mask |= (1 << 2);
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}
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if (val32 & (1 << 3)) {
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val32 &= ~(1 <<3);
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mask |= (1 << 3);
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}
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break;
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case ISOMSK:
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mask = 0x8F;
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break;
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case ISOBRC:
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case ISOBUF:
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/* check if we are in transmitting mode */
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if (s->regs[ISOCON>>2] & ISOCON_TR) {
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uint8_t ch = val32;
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qemu_chr_fe_write(s->chr, &ch, 1);
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s->regs[ISOCON>>2] &= ~ISOCON_TACT;
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mask = 0;
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} else
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mask = 0xFF;
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break;
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case ISODIO:
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case ISODMACON:
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mask = 3;
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break;
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case ISODMASTS:
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case ISODMAMSK:
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mask = 0x07;
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break;
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case ISODMABFAD:
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mask = 0xffffff;
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break;
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case ISODMABFLEN:
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mask = 0x1FF;
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break;
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case ISODMABFPT:
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mask = 0;
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break;
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case ISOTCON:
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mask = 0x0F;
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break;
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case ISOTMSK:
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mask = 1;
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break;
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case ISOTDAT:
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case ISOTRLD:
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mask = 0xFFFF;
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break;
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case ISONULL:
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mask = 0xFF;
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break;
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default:
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mask = 0;
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break;
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}
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s->regs[reg_idx] = (s->regs[reg_idx] & ~mask) | (val32 & mask);
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iso_slave_update_irq(s);
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}
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static const MemoryRegionOps iso_slave_ops = {
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.read = iso_slave_read,
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.write = iso_slave_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void iso_slave_rx(void *opaque, const uint8_t *buf, int size)
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{
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CC32IsoSlaveState *s = opaque;
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if (s->regs[ISOSTS>>2] & ISOSTS_RBF)
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s->regs[ISOSTS>>2] |= ISOSTS_OE;
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else
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s->regs[ISOSTS>>2] |= ISOSTS_RBF;
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s->regs[ISOBUF>>2] = *buf;
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iso_slave_update_irq(s);
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}
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static int iso_slave_can_rx(void *opaque)
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{
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CC32IsoSlaveState *s = opaque;
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/* check if we are in receive mode */
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if (s->regs[ISOCON>>2] & ISOCON_TR)
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return 0;
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return 1;
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}
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static void iso_slave_event(void *opaque, int event)
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{
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}
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static void iso_slave_reset(DeviceState *d)
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{
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CC32IsoSlaveState *s = container_of(d, CC32IsoSlaveState, busdev.qdev);
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int i;
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for (i = 0; i < NUM_REGS; i++) {
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switch (i << 2) {
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case ISOCON:
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case ISOSTS:
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case ISOBRC:
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case ISODIO:
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case ISOTMSK:
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s->regs[i] = 0x00000001;
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break;
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case ISOCON1:
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case ISODMAMSK:
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s->regs[i] = 0x00000007;
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break;
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case ISONULL:
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s->regs[i] = 0x00000060;
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break;
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default:
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s->regs[i] = 0;
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break;
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}
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}
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}
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static int iso_slave_init(SysBusDevice *dev)
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{
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CC32IsoSlaveState *s = FROM_SYSBUS(typeof(*s), dev);
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sysbus_init_irq(dev, &s->irq);
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memory_region_init_io(&s->iomem, &iso_slave_ops, s, "iso7816_slave", 0x64);
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sysbus_init_mmio(dev, &s->iomem);
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s->chr = qemu_char_get_next_serial();
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, iso_slave_can_rx, iso_slave_rx, iso_slave_event, s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_iso_slave = {
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.name = "cc32-iso-slave",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, CC32IsoSlaveState, NUM_REGS),
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VMSTATE_END_OF_LIST()
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},
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};
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static void iso_slave_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = iso_slave_init;
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dc->reset = iso_slave_reset;
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dc->vmsd = &vmstate_iso_slave;
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}
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static TypeInfo iso_slave_info = {
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.name = "cc32-iso-slave",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(CC32IsoSlaveState),
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.class_init = iso_slave_class_init,
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};
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static void iso_slave_register_types(void)
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{
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type_register_static(&iso_slave_info);
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}
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type_init(iso_slave_register_types);
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@ -0,0 +1,227 @@
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/*
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* ChipCity CC32RS512 Smart Card emulation
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*
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* Copyright (C) 2012 Harald Welte <laforge@gnumonks.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sysbus.h"
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#include "arm-misc.h"
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#include "devices.h"
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#include "boards.h"
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#include "exec-memory.h"
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enum cc32_sysc_reg {
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SCCM0 = 0x00,
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SCSYS = 0x04,
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SCCKOUT = 0x20,
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SCRSTFLG = 0x28,
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SCRSTEN = 0x2C,
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SCSFTRST = 0x30,
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SCRSTCON0 = 0x34,
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SCRSTCON4 = 0x38,
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SCSLEEP = 0x3C,
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SCGCON = 0x40,
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SCINTSTS = 0x44,
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SCINTEN = 0x48,
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SCGINT0 = 0x5C,
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SCGLEV = 0x64,
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SCWUT = 0x68,
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SCCM4 = 0x7C,
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};
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#define NUM_REGS (SCCM4 + 4)
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typedef struct cc32_sysc_state
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{
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t level;
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uint32_t irq_enabled;
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qemu_irq parent_irq;
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qemu_irq parent_fiq;
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} cc32_sysc_state;
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#define FIQ_MASK (1 << 8)
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#define IRQ_MASK ~FIQ_MASK
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static void cc32_sysc_update(cc32_sysc_state *s)
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{
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uint32_t flags;
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flags = (s->level & s->irq_enabled & IRQ_MASK);
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qemu_set_irq(s->parent_irq, flags != 0);
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flags = (s->level & s->irq_enabled & FIQ_MASK);
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qemu_set_irq(s->parent_fiq, flags != 0);
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}
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static void cc32_sysc_set_irq(void *opaque, int irq, int level)
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{
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cc32_sysc_state *s = (cc32_sysc_state *)opaque;
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if (level)
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s->level |= (1 << irq);
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else
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s->level &= ~(1 << irq);
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cc32_sysc_update(s);
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}
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static uint64_t cc32_sysc_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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cc32_sysc_state *s = (cc32_sysc_state *)opaque;
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switch (offset) {
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case SCINTSTS:
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return s->level & s->irq_enabled;
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case SCINTEN:
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return s->irq_enabled;
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}
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return 0;
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}
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static void cc32_sysc_write(void *opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size)
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{
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cc32_sysc_state *s = (cc32_sysc_state *)opaque;
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switch (offset) {
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case SCINTEN:
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s->irq_enabled = value;
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break;
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}
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cc32_sysc_update(s);
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}
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static const MemoryRegionOps cc32_sysc_ops = {
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.read = cc32_sysc_read,
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.write = cc32_sysc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int cc32_sysc_init(SysBusDevice *dev)
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{
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cc32_sysc_state *s = FROM_SYSBUS(cc32_sysc_state, dev);
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qdev_init_gpio_in(&dev->qdev, cc32_sysc_set_irq, 32);
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sysbus_init_irq(dev, &s->parent_irq);
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sysbus_init_irq(dev, &s->parent_fiq);
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memory_region_init_io(&s->iomem, &cc32_sysc_ops, s, "cc32-sysc", 8);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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static void cc32_sysc_reset(DeviceState *d)
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{
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cc32_sysc_state *s = container_of(d, cc32_sysc_state, busdev.qdev);
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s->irq_enabled = 0xFFFEF7FF;
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/* FIXME */
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}
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static void cc32_sysc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
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sdc->init = cc32_sysc_init;
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dc->reset = cc32_sysc_reset;
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}
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static TypeInfo cc32_sysc_info = {
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.name = "cc32-sysc",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(cc32_sysc_state),
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.class_init = cc32_sysc_class_init,
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};
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static void cc32_register_types(void)
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{
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type_register_static(&cc32_sysc_info);
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}
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type_init(cc32_register_types)
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struct arm_boot_info cc32rs512_binfo;
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static void cc32rs512_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *rsa_ram = g_new(MemoryRegion, 1);
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MemoryRegion *flash = g_new(MemoryRegion, 1);
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qemu_irq *cpu_irq;
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qemu_irq pic[32];
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DeviceState *dev;
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||||
int i;
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||||
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||||
if (!cpu_model)
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cpu_model = "arm926";
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||||
env = cpu_init(cpu_model);
|
||||
if (!env) {
|
||||
fprintf(stderr, "Unable to find CPU definition\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
memory_region_init_ram(flash, "cc32rs512.flash", 512*1024);
|
||||
memory_region_add_subregion(sysmem, 0, flash);
|
||||
|
||||
memory_region_init_ram(ram, "cc32rs512.ram", 16*1024);
|
||||
memory_region_add_subregion(sysmem, 0xc0000, ram);
|
||||
|
||||
memory_region_init_ram(rsa_ram, "cc32rs512.rsa_ram", 2*1024);
|
||||
memory_region_add_subregion(sysmem, 0xd4000, rsa_ram);
|
||||
|
||||
cc32rs512_binfo.ram_size = ram_size;
|
||||
cc32rs512_binfo.kernel_filename = kernel_filename;
|
||||
|
||||
cpu_irq = arm_pic_init_cpu(env);
|
||||
dev = sysbus_create_varargs("cc32-sysc", 0x0F0000,
|
||||
cpu_irq[ARM_PIC_CPU_IRQ],
|
||||
cpu_irq[ARM_PIC_CPU_FIQ], NULL);
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
pic[i] = qdev_get_gpio_in(dev, i);
|
||||
|
||||
sysbus_create_simple("cc32-iso-slave", 0x0F8800, pic[8]);
|
||||
|
||||
arm_load_kernel(env, &cc32rs512_binfo);
|
||||
}
|
||||
|
||||
static QEMUMachine cc32rs512_machine = {
|
||||
.name = "cc32rs512",
|
||||
.desc = "Chip City Smart Card (SC100)",
|
||||
.init = cc32rs512_init,
|
||||
.max_cpus = 1,
|
||||
};
|
||||
|
||||
static void cc32rs512_machine_init(void)
|
||||
{
|
||||
qemu_register_machine(&cc32rs512_machine);
|
||||
}
|
||||
|
||||
machine_init(cc32rs512_machine_init);
|
||||
Reference in New Issue