Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: Add Cortex-A15 CPU definition Add dummy implementation of generic timer cp15 registers arm: store the config_base_register during cpu_reset target-arm/helper.c: Don't assume softfloat int32 is 32 bits only target-arm: Fix implementation of TLB invalidate operations
This commit is contained in:
Blue Swirl
commit
9ec032d2ac
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@ -382,6 +382,7 @@ enum arm_features {
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ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
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ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
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ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
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ARM_FEATURE_GENERIC_TIMER,
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};
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static inline int arm_feature(CPUARMState *env, int feature)
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@ -432,6 +433,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
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#define ARM_CPUID_ARM11MPCORE 0x410fb022
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#define ARM_CPUID_CORTEXA8 0x410fc080
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#define ARM_CPUID_CORTEXA9 0x410fc090
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#define ARM_CPUID_CORTEXA15 0x412fc0f1
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#define ARM_CPUID_CORTEXM3 0x410fc231
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#define ARM_CPUID_ANY 0xffffffff
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@ -10,6 +10,16 @@
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#include "sysemu.h"
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static uint32_t cortexa15_cp15_c0_c1[8] = {
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0x00001131, 0x00011011, 0x02010555, 0x00000000,
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0x10201105, 0x20000000, 0x01240000, 0x02102211
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};
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static uint32_t cortexa15_cp15_c0_c2[8] = {
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0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0
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};
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static uint32_t cortexa9_cp15_c0_c1[8] =
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{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
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@ -158,6 +168,27 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
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env->cp15.c1_sys = 0x00c50078;
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break;
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case ARM_CPUID_CORTEXA15:
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set_feature(env, ARM_FEATURE_V7);
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set_feature(env, ARM_FEATURE_VFP4);
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set_feature(env, ARM_FEATURE_VFP_FP16);
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set_feature(env, ARM_FEATURE_NEON);
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set_feature(env, ARM_FEATURE_THUMB2EE);
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set_feature(env, ARM_FEATURE_ARM_DIV);
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set_feature(env, ARM_FEATURE_V7MP);
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set_feature(env, ARM_FEATURE_GENERIC_TIMER);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
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memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
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memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
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env->cp15.c0_cachetype = 0x8444c004;
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env->cp15.c0_clid = 0x0a200023;
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env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
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env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
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env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
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env->cp15.c1_sys = 0x00c50078;
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break;
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case ARM_CPUID_CORTEXM3:
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set_feature(env, ARM_FEATURE_V7);
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set_feature(env, ARM_FEATURE_M);
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@ -255,6 +286,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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void cpu_reset(CPUARMState *env)
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{
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uint32_t id;
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uint32_t tmp = 0;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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@ -262,9 +294,11 @@ void cpu_reset(CPUARMState *env)
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}
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id = env->cp15.c0_cpuid;
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tmp = env->cp15.c15_config_base_address;
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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if (id)
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cpu_reset_model_id(env, id);
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env->cp15.c15_config_base_address = tmp;
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#if defined (CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR;
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/* For user mode we must enable access to coprocessors */
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@ -413,6 +447,7 @@ static const struct arm_cpu_t arm_cpu_names[] = {
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{ ARM_CPUID_CORTEXM3, "cortex-m3"},
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{ ARM_CPUID_CORTEXA8, "cortex-a8"},
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{ ARM_CPUID_CORTEXA9, "cortex-a9"},
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{ ARM_CPUID_CORTEXA15, "cortex-a15" },
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{ ARM_CPUID_TI925T, "ti925t" },
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{ ARM_CPUID_PXA250, "pxa250" },
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{ ARM_CPUID_SA1100, "sa1100" },
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@ -667,8 +702,6 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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#else
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extern int semihosting_enabled;
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/* Map CPU modes onto saved register banks. */
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static inline int bank_number(CPUState *env, int mode)
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{
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@ -1610,18 +1643,17 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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break;
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case 8: /* MMU TLB control. */
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switch (op2) {
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case 0: /* Invalidate all. */
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tlb_flush(env, 0);
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case 0: /* Invalidate all (TLBIALL) */
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tlb_flush(env, 1);
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break;
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case 1: /* Invalidate single TLB entry. */
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case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
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tlb_flush_page(env, val & TARGET_PAGE_MASK);
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break;
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case 2: /* Invalidate on ASID. */
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case 2: /* Invalidate by ASID (TLBIASID) */
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tlb_flush(env, val == 0);
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break;
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case 3: /* Invalidate single entry on MVA. */
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/* ??? This is like case 1, but ignores ASID. */
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tlb_flush(env, 1);
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case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
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tlb_flush_page(env, val & TARGET_PAGE_MASK);
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break;
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default:
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goto bad_reg;
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@ -1762,7 +1794,11 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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goto bad_reg;
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}
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break;
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case 14: /* Reserved. */
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case 14: /* Generic timer */
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if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
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/* Dummy implementation: RAZ/WI for all */
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break;
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}
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goto bad_reg;
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case 15: /* Implementation specific. */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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@ -1939,6 +1975,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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case ARM_CPUID_CORTEXA8:
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return 2;
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case ARM_CPUID_CORTEXA9:
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case ARM_CPUID_CORTEXA15:
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return 0;
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default:
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goto bad_reg;
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@ -2059,11 +2096,26 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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goto bad_reg;
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}
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case 1: /* L2 cache */
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if (crm != 0) {
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/* L2 Lockdown and Auxiliary control. */
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switch (op2) {
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case 0:
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/* L2 cache lockdown (A8 only) */
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return 0;
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case 2:
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/* L2 cache auxiliary control (A8) or control (A15) */
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if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) {
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/* Linux wants the number of processors from here.
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* Might as well set the interrupt-controller bit too.
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*/
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return ((smp_cpus - 1) << 24) | (1 << 23);
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}
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return 0;
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case 3:
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/* L2 cache extended control (A15) */
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return 0;
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default:
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goto bad_reg;
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}
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/* L2 Lockdown and Auxiliary control. */
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return 0;
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default:
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goto bad_reg;
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}
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@ -2132,7 +2184,11 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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default:
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goto bad_reg;
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}
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case 14: /* Reserved. */
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case 14: /* Generic timer */
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if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
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/* Dummy implementation: RAZ/WI for all */
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return 0;
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}
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goto bad_reg;
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case 15: /* Implementation specific. */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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@ -2786,7 +2842,7 @@ DO_VFP_cmp(d, float64)
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float##fsz HELPER(name)(uint32_t x, void *fpstp) \
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{ \
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float_status *fpst = fpstp; \
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return sign##int32_to_##float##fsz(x, fpst); \
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return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
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}
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#define CONV_FTOI(name, fsz, sign, round) \
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