Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu. It's far from perfect - it's missing a number of POWER7 features so far, including any support for VSX or decimal floating point instructions. However, it's close enough to boot a kernel with the POWER7 PVR. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson
Alexander Graf
parent
cdaee00633
commit
9d52e9079d
35
hw/ppc.c
35
hw/ppc.c
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@ -247,6 +247,41 @@ void ppc970_irq_init (CPUState *env)
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env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
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PPC970_INPUT_NB);
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}
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/* POWER7 internal IRQ controller */
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static void power7_set_irq (void *opaque, int pin, int level)
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{
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CPUState *env = opaque;
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int cur_level;
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LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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env, pin, level);
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cur_level = (env->irq_input_state >> pin) & 1;
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switch (pin) {
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case POWER7_INPUT_INT:
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/* Level sensitive - active high */
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LOG_IRQ("%s: set the external IRQ state to %d\n",
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__func__, level);
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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break;
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default:
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/* Unknown pin - do nothing */
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LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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return;
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}
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if (level) {
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env->irq_input_state |= 1 << pin;
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} else {
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env->irq_input_state &= ~(1 << pin);
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}
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}
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void ppcPOWER7_irq_init (CPUState *env)
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{
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env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env,
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POWER7_INPUT_NB);
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}
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#endif /* defined(TARGET_PPC64) */
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/* PowerPC 40x internal IRQ controller */
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1
hw/ppc.h
1
hw/ppc.h
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@ -36,6 +36,7 @@ void ppc40x_irq_init (CPUState *env);
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void ppce500_irq_init (CPUState *env);
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void ppc6xx_irq_init (CPUState *env);
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void ppc970_irq_init (CPUState *env);
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void ppcPOWER7_irq_init (CPUState *env);
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/* PPC machines for OpenBIOS */
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enum {
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@ -119,6 +119,8 @@ enum powerpc_mmu_t {
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POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
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/* 620 variant (no segment exceptions) */
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POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
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/* Architecture 2.06 variant */
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POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
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#endif /* defined(TARGET_PPC64) */
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};
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@ -154,6 +156,8 @@ enum powerpc_excp_t {
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#if defined(TARGET_PPC64)
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/* PowerPC 970 exception model */
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POWERPC_EXCP_970,
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/* POWER7 exception model */
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POWERPC_EXCP_POWER7,
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#endif /* defined(TARGET_PPC64) */
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};
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@ -289,6 +293,8 @@ enum powerpc_input_t {
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PPC_FLAGS_INPUT_405,
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/* PowerPC 970 bus */
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PPC_FLAGS_INPUT_970,
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/* PowerPC POWER7 bus */
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PPC_FLAGS_INPUT_POWER7,
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/* PowerPC 401 bus */
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PPC_FLAGS_INPUT_401,
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/* Freescale RCPU bus */
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@ -1001,6 +1007,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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#define SPR_HSPRG1 (0x131)
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#define SPR_HDSISR (0x132)
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#define SPR_HDAR (0x133)
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#define SPR_SPURR (0x134)
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#define SPR_BOOKE_DBCR0 (0x134)
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#define SPR_IBCR (0x135)
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#define SPR_PURR (0x135)
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@ -1625,6 +1632,15 @@ enum {
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PPC970_INPUT_THINT = 6,
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PPC970_INPUT_NB,
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};
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enum {
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/* POWER7 input pins */
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POWER7_INPUT_INT = 0,
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/* POWER7 probably has other inputs, but we don't care about them
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* for any existing machine. We can wire these up when we need
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* them */
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POWER7_INPUT_NB,
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};
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#endif
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/* Hardware exceptions definitions */
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@ -1200,6 +1200,7 @@ static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_620:
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case POWERPC_MMU_64B:
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case POWERPC_MMU_2_06:
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/* Real address are 60 bits long */
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ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
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ctx->prot |= PAGE_WRITE;
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@ -1277,6 +1278,7 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_620:
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case POWERPC_MMU_64B:
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case POWERPC_MMU_2_06:
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#endif
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if (ret < 0) {
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/* We didn't match any BAT entry or don't have BATs */
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@ -1376,6 +1378,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_620:
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case POWERPC_MMU_64B:
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case POWERPC_MMU_2_06:
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#endif
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env->exception_index = POWERPC_EXCP_ISI;
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env->error_code = 0x40000000;
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@ -1485,6 +1488,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_620:
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case POWERPC_MMU_64B:
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case POWERPC_MMU_2_06:
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#endif
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env->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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@ -1808,6 +1812,7 @@ void ppc_tlb_invalidate_all (CPUPPCState *env)
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_620:
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case POWERPC_MMU_64B:
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case POWERPC_MMU_2_06:
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#endif /* defined(TARGET_PPC64) */
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tlb_flush(env, 1);
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break;
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@ -1875,6 +1880,7 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_620:
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case POWERPC_MMU_64B:
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case POWERPC_MMU_2_06:
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/* tlbie invalidate TLBs for all segments */
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/* XXX: given the fact that there are too many segments to invalidate,
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* and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
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@ -61,6 +61,7 @@ void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
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PPC_IRQ_INIT_FN(40x);
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PPC_IRQ_INIT_FN(6xx);
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PPC_IRQ_INIT_FN(970);
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PPC_IRQ_INIT_FN(POWER7);
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PPC_IRQ_INIT_FN(e500);
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/* Generic callbacks:
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@ -3131,6 +3132,35 @@ static void init_excp_970 (CPUPPCState *env)
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env->hreset_vector = 0x0000000000000100ULL;
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#endif
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}
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static void init_excp_POWER7 (CPUPPCState *env)
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{
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#if !defined(CONFIG_USER_ONLY)
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env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
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env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
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env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
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env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
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env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
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env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
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env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
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env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
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env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
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env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
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env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
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env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
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env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
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env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
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env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
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env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
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env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
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env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
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env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
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env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
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env->hreset_excp_prefix = 0;
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/* Hardware reset vector */
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env->hreset_vector = 0x0000000000000100ULL;
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#endif
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}
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#endif
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/*****************************************************************************/
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@ -6312,6 +6342,78 @@ static void init_proc_970MP (CPUPPCState *env)
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vscr_init(env, 0x00010000);
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}
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#if defined(TARGET_PPC64)
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/* POWER7 */
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#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
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PPC_FLOAT_STFIWX | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
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PPC_MEM_SYNC | PPC_MEM_EIEIO | \
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
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PPC_64B | PPC_ALTIVEC | \
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PPC_SEGMENT_64B | PPC_SLBI | \
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PPC_POPCNTB | PPC_POPCNTWD)
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#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
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#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
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#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
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#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
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#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
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#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
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POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
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POWERPC_FLAG_BUS_CLK)
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#define check_pow_POWER7 check_pow_nocheck
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static void init_proc_POWER7 (CPUPPCState *env)
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{
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gen_spr_ne_601(env);
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gen_spr_7xx(env);
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/* Time base */
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gen_tbl(env);
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#if !defined(CONFIG_USER_ONLY)
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/* PURR & SPURR: Hack - treat these as aliases for the TB for now */
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spr_register(env, SPR_PURR, "PURR",
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&spr_read_purr, SPR_NOACCESS,
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&spr_read_purr, SPR_NOACCESS,
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0x00000000);
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spr_register(env, SPR_SPURR, "SPURR",
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&spr_read_purr, SPR_NOACCESS,
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&spr_read_purr, SPR_NOACCESS,
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0x00000000);
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#endif /* !CONFIG_USER_ONLY */
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/* Memory management */
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/* XXX : not implemented */
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spr_register(env, SPR_MMUCFG, "MMUCFG",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, SPR_NOACCESS,
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0x00000000); /* TOFIX */
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/* XXX : not implemented */
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spr_register(env, SPR_CTRL, "SPR_CTRLT",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x80800000);
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spr_register(env, SPR_UCTRL, "SPR_CTRLF",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x80800000);
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spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
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&spr_read_generic, &spr_write_generic,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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#if !defined(CONFIG_USER_ONLY)
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env->slb_nr = 32;
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#endif
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init_excp_POWER7(env);
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env->dcache_line_size = 128;
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env->icache_line_size = 128;
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/* Allocate hardware IRQ controller */
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ppcPOWER7_irq_init(env);
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/* Can't find information on what this should be on reset. This
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* value is the one used by 74xx processors. */
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vscr_init(env, 0x00010000);
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}
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#endif /* TARGET_PPC64 */
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/* PowerPC 620 */
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#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
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@ -7034,6 +7136,8 @@ enum {
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CPU_POWERPC_POWER6 = 0x003E0000,
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CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
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CPU_POWERPC_POWER6A = 0x0F000002,
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#define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
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CPU_POWERPC_POWER7_v20 = 0x003F0200,
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CPU_POWERPC_970 = 0x00390202,
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#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
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CPU_POWERPC_970FX_v10 = 0x00391100,
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@ -8836,6 +8940,9 @@ static const ppc_def_t ppc_defs[] = {
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/* POWER6A */
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POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
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#endif
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/* POWER7 */
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POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
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POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
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/* PowerPC 970 */
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POWERPC_DEF("970", CPU_POWERPC_970, 970),
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/* PowerPC 970FX (G5) */
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