FDC fix 3/10 (Hervé Poussineau):
- Fixes status A and status B registers. It removes one Sun4m mutation. Also removes the internal FD_CTRL_INTR flag. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4283 c046a42c-6fe2-441c-8c8c-71466251a162
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blueswir1
parent
746d6de7fe
commit
8c6a4d7742
91
hw/fdc.c
91
hw/fdc.c
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@ -323,6 +323,7 @@ static int fdctrl_transfer_handler (void *opaque, int nchan,
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int dma_pos, int dma_len);
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static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status);
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static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
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static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
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@ -339,7 +340,6 @@ enum {
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FD_CTRL_RESET = 0x02,
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FD_CTRL_SLEEP = 0x04, /* XXX: suppress that */
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FD_CTRL_BUSY = 0x08, /* dma transfer in progress */
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FD_CTRL_INTR = 0x10,
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};
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enum {
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@ -361,8 +361,8 @@ enum {
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};
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enum {
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FD_REG_0 = 0x00,
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FD_REG_STATUSB = 0x01,
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FD_REG_SRA = 0x00,
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FD_REG_SRB = 0x01,
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FD_REG_DOR = 0x02,
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FD_REG_TDR = 0x03,
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FD_REG_MSR = 0x04,
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@ -420,6 +420,26 @@ enum {
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FD_SR0_RDYCHG = 0xc0,
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};
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enum {
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FD_SRA_DIR = 0x01,
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FD_SRA_nWP = 0x02,
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FD_SRA_nINDX = 0x04,
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FD_SRA_HDSEL = 0x08,
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FD_SRA_nTRK0 = 0x10,
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FD_SRA_STEP = 0x20,
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FD_SRA_nDRV2 = 0x40,
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FD_SRA_INTPEND = 0x80,
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};
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enum {
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FD_SRB_MTR0 = 0x01,
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FD_SRB_MTR1 = 0x02,
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FD_SRB_WGATE = 0x04,
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FD_SRB_RDATA = 0x08,
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FD_SRB_WDATA = 0x10,
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FD_SRB_DR0 = 0x20,
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};
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enum {
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FD_DOR_SELMASK = 0x01,
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FD_DOR_nRESET = 0x04,
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@ -472,6 +492,8 @@ struct fdctrl_t {
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target_phys_addr_t io_base;
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/* Controller state */
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QEMUTimer *result_timer;
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uint8_t sra;
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uint8_t srb;
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uint8_t state;
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uint8_t dma_en;
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uint8_t cur_drv;
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@ -506,15 +528,10 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg)
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uint32_t retval;
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switch (reg & 0x07) {
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case FD_REG_0:
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if (fdctrl->sun4m) {
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// Identify to Linux as S82078B
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retval = fdctrl_read_statusB(fdctrl);
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} else {
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retval = (uint32_t)(-1);
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}
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case FD_REG_SRA:
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retval = fdctrl_read_statusA(fdctrl);
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break;
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case FD_REG_STATUSB:
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case FD_REG_SRB:
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retval = fdctrl_read_statusB(fdctrl);
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break;
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case FD_REG_DOR:
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@ -617,6 +634,9 @@ static void fdc_save (QEMUFile *f, void *opaque)
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{
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fdctrl_t *s = opaque;
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/* Controller state */
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qemu_put_8s(f, &s->sra);
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qemu_put_8s(f, &s->srb);
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qemu_put_8s(f, &s->state);
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qemu_put_8s(f, &s->dma_en);
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qemu_put_8s(f, &s->cur_drv);
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@ -661,6 +681,9 @@ static int fdc_load (QEMUFile *f, void *opaque, int version_id)
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if (version_id != 1)
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return -EINVAL;
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/* Controller state */
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qemu_get_8s(f, &s->sra);
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qemu_get_8s(f, &s->srb);
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qemu_get_8s(f, &s->state);
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qemu_get_8s(f, &s->dma_en);
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qemu_get_8s(f, &s->cur_drv);
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@ -712,9 +735,11 @@ int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
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/* Change IRQ state */
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static void fdctrl_reset_irq (fdctrl_t *fdctrl)
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{
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if (!(fdctrl->sra & FD_SRA_INTPEND))
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return;
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FLOPPY_DPRINTF("Reset interrupt\n");
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qemu_set_irq(fdctrl->irq, 0);
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fdctrl->state &= ~FD_CTRL_INTR;
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fdctrl->sra &= ~FD_SRA_INTPEND;
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}
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static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status)
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@ -725,9 +750,9 @@ static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status)
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fdctrl->int_status = status;
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return;
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}
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if (~(fdctrl->state & FD_CTRL_INTR)) {
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if (!(fdctrl->sra & FD_SRA_INTPEND)) {
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qemu_set_irq(fdctrl->irq, 1);
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fdctrl->state |= FD_CTRL_INTR;
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fdctrl->sra |= FD_SRA_INTPEND;
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}
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FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", status);
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fdctrl->int_status = status;
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@ -741,6 +766,10 @@ static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
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FLOPPY_DPRINTF("reset controller\n");
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fdctrl_reset_irq(fdctrl);
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/* Initialise controller */
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fdctrl->sra = 0;
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fdctrl->srb = 0xc0;
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if (!fdctrl->drives[1].bs)
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fdctrl->sra |= FD_SRA_nDRV2;
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fdctrl->cur_drv = 0;
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/* FIFO state */
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fdctrl->data_pos = 0;
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@ -769,11 +798,24 @@ static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
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return fdctrl->cur_drv == 0 ? drv0(fdctrl) : drv1(fdctrl);
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}
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/* Status A register : 0x00 (read-only) */
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static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
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{
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uint32_t retval = fdctrl->sra;
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FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
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return retval;
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}
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/* Status B register : 0x01 (read-only) */
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static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
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{
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FLOPPY_DPRINTF("status register: 0x00\n");
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return 0;
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uint32_t retval = fdctrl->srb;
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FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
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return retval;
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}
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/* Digital output register : 0x02 */
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@ -809,6 +851,23 @@ static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
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}
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}
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FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
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/* Motors */
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if (value & FD_DOR_MOTEN0)
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fdctrl->srb |= FD_SRB_MTR0;
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else
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fdctrl->srb &= ~FD_SRB_MTR0;
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if (value & FD_DOR_MOTEN1)
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fdctrl->srb |= FD_SRB_MTR1;
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else
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fdctrl->srb &= ~FD_SRB_MTR1;
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/* Drive */
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if (value & 1)
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fdctrl->srb |= FD_SRB_DR0;
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else
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fdctrl->srb &= ~FD_SRB_DR0;
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/* Drive motors state indicators */
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if (value & FD_DOR_MOTEN1)
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fd_start(drv1(fdctrl));
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