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microblaze: Trap on divizions by zero. 

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Edgar E. Iglesias 2009-09-03 12:52:01 +02:00
parent ee7dbcf834
commit 821ebb33e4
2 changed files with 6 additions and 2 deletions
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7
target-microblaze/op_helper.c
View File

@ -167,7 +167,12 @@ static inline int div_prepare(uint32_t a, uint32_t b)
{
if (b == 0) {
env->sregs[SR_MSR] |= MSR_DZ;
/* FIXME: Raise the div by zero exception. */
if ((env->sregs[SR_MSR] & MSR_EE)
&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_DIVZERO;
helper_raise_exception(EXCP_HW_EXCP);
}
return 0;
}
env->sregs[SR_MSR] &= ~MSR_DZ;

1
target-microblaze/translate.c
View File

@ -616,7 +616,6 @@ static void dec_div(DisasContext *dc)
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
/* FIXME: support div by zero exceptions. */
if (u)
gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
else