i8259: Convert to qdev
This key cleanup step requires to move the IRQ debugging bit from i8259_set_irq directly to the per-PIC pic_set_irq, to pass the PIC parameters (I/O base, ELCR address and mask, master/slave mode) as qdev properties, and to interconnect the PICs with their environment via GPIO pins. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Jan Kiszka
Blue Swirl
parent
6835678c25
commit
747c70af78
157
hw/i8259.c
157
hw/i8259.c
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@ -41,6 +41,7 @@
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//#define DEBUG_IRQ_COUNT
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struct PicState {
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ISADevice dev;
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uint8_t last_irr; /* edge detection */
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uint8_t irr; /* interrupt request register */
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uint8_t imr; /* interrupt mask register */
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@ -58,8 +59,10 @@ struct PicState {
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uint8_t single_mode; /* true if slave pic is not initialized */
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uint8_t elcr; /* PIIX edge/trigger selection*/
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uint8_t elcr_mask;
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qemu_irq int_out;
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bool master; /* reflects /SP input pin */
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qemu_irq int_out[1];
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uint32_t master; /* reflects /SP input pin */
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uint32_t iobase;
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uint32_t elcr_addr;
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MemoryRegion base_io;
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MemoryRegion elcr_io;
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};
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@ -70,6 +73,9 @@ static int irq_level[16];
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#ifdef DEBUG_IRQ_COUNT
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static uint64_t irq_count[16];
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#endif
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#ifdef DEBUG_IRQ_LATENCY
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static int64_t irq_time[16];
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#endif
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PicState *isa_pic;
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static PicState *slave_pic;
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@ -122,17 +128,39 @@ static void pic_update_irq(PicState *s)
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if (irq >= 0) {
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DPRINTF("pic%d: imr=%x irr=%x padd=%d\n",
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s->master ? 0 : 1, s->imr, s->irr, s->priority_add);
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qemu_irq_raise(s->int_out);
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qemu_irq_raise(s->int_out[0]);
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} else {
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qemu_irq_lower(s->int_out);
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qemu_irq_lower(s->int_out[0]);
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}
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}
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/* set irq level. If an edge is detected, then the IRR is set to 1 */
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static void pic_set_irq1(PicState *s, int irq, int level)
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static void pic_set_irq(void *opaque, int irq, int level)
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{
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int mask;
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mask = 1 << irq;
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PicState *s = opaque;
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int mask = 1 << irq;
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) || \
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defined(DEBUG_IRQ_LATENCY)
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int irq_index = s->master ? irq : irq + 8;
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#endif
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
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if (level != irq_level[irq_index]) {
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DPRINTF("pic_set_irq: irq=%d level=%d\n", irq_index, level);
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irq_level[irq_index] = level;
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#ifdef DEBUG_IRQ_COUNT
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if (level == 1) {
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irq_count[irq_index]++;
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}
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#endif
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}
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#endif
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#ifdef DEBUG_IRQ_LATENCY
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if (level) {
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irq_time[irq_index] = qemu_get_clock_ns(vm_clock);
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}
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#endif
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if (s->elcr & mask) {
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/* level triggered */
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if (level) {
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@ -156,32 +184,6 @@ static void pic_set_irq1(PicState *s, int irq, int level)
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pic_update_irq(s);
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}
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#ifdef DEBUG_IRQ_LATENCY
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int64_t irq_time[16];
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#endif
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static void i8259_set_irq(void *opaque, int irq, int level)
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{
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PicState *s = irq <= 7 ? isa_pic : slave_pic;
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#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
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if (level != irq_level[irq]) {
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DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
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irq_level[irq] = level;
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#ifdef DEBUG_IRQ_COUNT
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if (level == 1)
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irq_count[irq]++;
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#endif
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}
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#endif
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#ifdef DEBUG_IRQ_LATENCY
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if (level) {
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irq_time[irq] = qemu_get_clock_ns(vm_clock);
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}
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#endif
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pic_set_irq1(s, irq & 7, level);
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}
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/* acknowledge interrupt 'irq' */
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static void pic_intack(PicState *s, int irq)
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{
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@ -258,9 +260,9 @@ static void pic_init_reset(PicState *s)
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pic_update_irq(s);
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}
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static void pic_reset(void *opaque)
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static void pic_reset(DeviceState *dev)
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{
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PicState *s = opaque;
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PicState *s = container_of(dev, PicState, dev.qdev);
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pic_init_reset(s);
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s->elcr = 0;
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@ -447,23 +449,24 @@ static const MemoryRegionOps pic_elcr_ioport_ops = {
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},
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};
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/* XXX: add generic master/slave system */
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static void pic_init(int io_addr, int elcr_addr, PicState *s, qemu_irq int_out,
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bool master)
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static int pic_initfn(ISADevice *dev)
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{
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s->int_out = int_out;
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s->master = master;
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PicState *s = DO_UPCAST(PicState, dev, dev);
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memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
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memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
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isa_register_ioport(NULL, &s->base_io, io_addr);
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if (elcr_addr >= 0) {
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isa_register_ioport(NULL, &s->elcr_io, elcr_addr);
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isa_register_ioport(NULL, &s->base_io, s->iobase);
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if (s->elcr_addr != -1) {
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isa_register_ioport(NULL, &s->elcr_io, s->elcr_addr);
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}
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vmstate_register(NULL, io_addr, &vmstate_pic, s);
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qemu_register_reset(pic_reset, s);
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qdev_init_gpio_out(&dev->qdev, s->int_out, ARRAY_SIZE(s->int_out));
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qdev_init_gpio_in(&dev->qdev, pic_set_irq, 8);
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qdev_set_legacy_instance_id(&dev->qdev, s->iobase, 1);
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return 0;
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}
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void pic_info(Monitor *mon)
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@ -503,20 +506,60 @@ void irq_info(Monitor *mon)
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qemu_irq *i8259_init(qemu_irq parent_irq)
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{
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qemu_irq *irqs;
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PicState *s;
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qemu_irq *irq_set;
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ISADevice *dev;
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int i;
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irqs = qemu_allocate_irqs(i8259_set_irq, NULL, 16);
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irq_set = g_malloc(ISA_NUM_IRQS * sizeof(qemu_irq));
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s = g_malloc0(sizeof(PicState));
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pic_init(0x20, 0x4d0, s, parent_irq, true);
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s->elcr_mask = 0xf8;
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isa_pic = s;
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dev = isa_create("isa-i8259");
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qdev_prop_set_uint32(&dev->qdev, "iobase", 0x20);
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qdev_prop_set_uint32(&dev->qdev, "elcr_addr", 0x4d0);
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qdev_prop_set_uint8(&dev->qdev, "elcr_mask", 0xf8);
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qdev_prop_set_bit(&dev->qdev, "master", true);
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qdev_init_nofail(&dev->qdev);
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s = g_malloc0(sizeof(PicState));
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pic_init(0xa0, 0x4d1, s, irqs[2], false);
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s->elcr_mask = 0xde;
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slave_pic = s;
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qdev_connect_gpio_out(&dev->qdev, 0, parent_irq);
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for (i = 0 ; i < 8; i++) {
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irq_set[i] = qdev_get_gpio_in(&dev->qdev, i);
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}
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return irqs;
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isa_pic = DO_UPCAST(PicState, dev, dev);
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dev = isa_create("isa-i8259");
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qdev_prop_set_uint32(&dev->qdev, "iobase", 0xa0);
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qdev_prop_set_uint32(&dev->qdev, "elcr_addr", 0x4d1);
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qdev_prop_set_uint8(&dev->qdev, "elcr_mask", 0xde);
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qdev_init_nofail(&dev->qdev);
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qdev_connect_gpio_out(&dev->qdev, 0, irq_set[2]);
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for (i = 0 ; i < 8; i++) {
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irq_set[i + 8] = qdev_get_gpio_in(&dev->qdev, i);
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}
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slave_pic = DO_UPCAST(PicState, dev, dev);
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return irq_set;
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}
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static ISADeviceInfo i8259_info = {
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.qdev.name = "isa-i8259",
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.qdev.size = sizeof(PicState),
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.qdev.vmsd = &vmstate_pic,
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.qdev.reset = pic_reset,
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.qdev.no_user = 1,
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.init = pic_initfn,
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.qdev.props = (Property[]) {
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DEFINE_PROP_HEX32("iobase", PicState, iobase, -1),
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DEFINE_PROP_HEX32("elcr_addr", PicState, elcr_addr, -1),
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DEFINE_PROP_HEX8("elcr_mask", PicState, elcr_mask, -1),
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DEFINE_PROP_BIT("master", PicState, master, 0, false),
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DEFINE_PROP_END_OF_LIST(),
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},
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};
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static void pic_register(void)
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{
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isa_qdev_register(&i8259_info);
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}
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device_init(pic_register)
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