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Register reset handlers 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6136 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-12-28 18:27:10 +00:00
parent b4e237aae7
commit 6e6b736313
9 changed files with 159 additions and 19 deletions
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4
hw/adb.c
View File

@ -122,6 +122,8 @@ ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
d->devreq = devreq;
d->devreset = devreset;
d->opaque = opaque;
qemu_register_reset(devreset, d);
d->devreset(d);
return d;
}
@ -278,7 +280,6 @@ void adb_kbd_init(ADBBusState *bus)
s = qemu_mallocz(sizeof(KBDState));
d = adb_register_device(bus, ADB_KEYBOARD, adb_kbd_request,
adb_kbd_reset, s);
adb_kbd_reset(d);
qemu_add_kbd_event_handler(adb_kbd_put_keycode, d);
}
@ -420,6 +421,5 @@ void adb_mouse_init(ADBBusState *bus)
s = qemu_mallocz(sizeof(MouseState));
d = adb_register_device(bus, ADB_MOUSE, adb_mouse_request,
adb_mouse_reset, s);
adb_mouse_reset(d);
qemu_add_mouse_event_handler(adb_mouse_event, d, 0, "QEMU ADB Mouse");
}

35
hw/cuda.c
View File

@ -633,6 +633,33 @@ static CPUReadMemoryFunc *cuda_read[] = {
&cuda_readl,
};
static void cuda_reset(void *opaque)
{
CUDAState *s = opaque;
s->b = 0;
s->a = 0;
s->dirb = 0;
s->dira = 0;
s->sr = 0;
s->acr = 0;
s->pcr = 0;
s->ifr = 0;
s->ier = 0;
// s->ier = T1_INT | SR_INT;
s->anh = 0;
s->data_in_size = 0;
s->data_in_index = 0;
s->data_out_index = 0;
s->autopoll = 0;
s->timers[0].latch = 0xffff;
set_counter(s, &s->timers[0], 0xffff);
s->timers[1].latch = 0;
set_counter(s, &s->timers[1], 0xffff);
}
void cuda_init (int *cuda_mem_index, qemu_irq irq)
{
CUDAState *s = &cuda_state;
@ -641,15 +668,11 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->timers[0].index = 0;
s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
s->timers[0].latch = 0xffff;
set_counter(s, &s->timers[0], 0xffff);
s->timers[1].index = 1;
s->timers[1].latch = 0;
// s->ier = T1_INT | SR_INT;
s->ier = 0;
set_counter(s, &s->timers[1], 0xffff);
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
qemu_register_reset(cuda_reset, s);
cuda_reset(s);
}

7
hw/grackle_pci.c
View File

@ -105,6 +105,10 @@ static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
qemu_set_irq(pic[irq_num + 0x15], level);
}
static void pci_grackle_reset(void *opaque)
{
}
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
{
GrackleState *s;
@ -160,5 +164,8 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
d->config[0x26] = 0x00; // prefetchable_memory_limit
d->config[0x27] = 0x85;
#endif
qemu_register_reset(pci_grackle_reset, d);
pci_grackle_reset(d);
return s->bus;
}

20
hw/heathrow_pic.c
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@ -165,17 +165,33 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level)
heathrow_pic_update(s);
}
static void heathrow_pic_reset_one(HeathrowPIC *s)
{
memset(s, '\0', sizeof(HeathrowPIC));
}
static void heathrow_pic_reset(void *opaque)
{
HeathrowPICS *s = opaque;
heathrow_pic_reset_one(&s->pics[0]);
heathrow_pic_reset_one(&s->pics[1]);
s->pics[0].level_triggered = 0;
s->pics[1].level_triggered = 0x1ff00000;
}
qemu_irq *heathrow_pic_init(int *pmem_index,
int nb_cpus, qemu_irq **irqs)
{
HeathrowPICS *s;
s = qemu_mallocz(sizeof(HeathrowPICS));
s->pics[0].level_triggered = 0;
s->pics[1].level_triggered = 0x1ff00000;
/* only 1 CPU */
s->irqs = irqs[0];
*pmem_index = cpu_register_io_memory(0, pic_read, pic_write, s);
qemu_register_reset(heathrow_pic_reset, s);
heathrow_pic_reset(s);
return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
}

22
hw/ide.c
View File

@ -3084,6 +3084,15 @@ static void cmd646_set_irq(void *opaque, int channel, int level)
cmd646_update_irq(d);
}
static void cmd646_reset(void *opaque)
{
PCIIDEState *d = opaque;
unsigned int i;
for (i = 0; i < 2; i++)
ide_dma_cancel(&d->bmdma[i]);
}
/* CMD646 PCI IDE controller */
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
int secondary_ide_enabled)
@ -3135,6 +3144,9 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]);
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
qemu_register_reset(cmd646_reset, d);
cmd646_reset(d);
}
static void pci_ide_save(QEMUFile* f, void *opaque)
@ -3405,6 +3417,14 @@ static CPUReadMemoryFunc *pmac_ide_read[] = {
pmac_ide_readl,
};
static void pmac_ide_reset(void *opaque)
{
IDEState *s = (IDEState *)opaque;
ide_reset(&s[0]);
ide_reset(&s[1]);
}
/* hd_table must contain 4 block drivers */
/* PowerMac uses memory mapped registers, not I/O. Return the memory
I/O index to access the ide. */
@ -3418,6 +3438,8 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
pmac_ide_write, &ide_if[0]);
qemu_register_reset(pmac_ide_reset, &ide_if[0]);
pmac_ide_reset(&ide_if[0]);
return pmac_ide_memory;
}

4
hw/m48t59.c
View File

@ -604,6 +604,8 @@ static void m48t59_reset(void *opaque)
{
m48t59_t *NVRAM = opaque;
NVRAM->addr = 0;
NVRAM->lock = 0;
if (NVRAM->alrm_timer != NULL)
qemu_del_timer(NVRAM->alrm_timer);
@ -630,7 +632,6 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
s->IRQ = IRQ;
s->size = size;
s->io_base = io_base;
s->addr = 0;
s->type = type;
if (io_base != 0) {
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
@ -644,7 +645,6 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
}
s->lock = 0;
qemu_get_timedate(&s->alarm, 0);
qemu_register_reset(m48t59_reset, s);

6
hw/mac_dbdma.c
View File

@ -88,7 +88,13 @@ static CPUReadMemoryFunc *dbdma_read[] = {
&dbdma_readl,
};
static void dbdma_reset(void *opaque)
{
}
void dbdma_init (int *dbdma_mem_index)
{
*dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
qemu_register_reset(dbdma_reset, NULL);
dbdma_reset(NULL);
}

6
hw/mac_nvram.c
View File

@ -104,6 +104,10 @@ static CPUReadMemoryFunc *nvram_read[] = {
&macio_nvram_readb,
};
static void macio_nvram_reset(void *opaque)
{
}
MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
{
MacIONVRAMState *s;
@ -120,6 +124,8 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
*mem_index = s->mem_index;
qemu_register_reset(macio_nvram_reset, s);
macio_nvram_reset(s);
return s;
}

74
hw/vga.c
View File

@ -1826,10 +1826,73 @@ static void vga_invalidate_display(void *opaque)
s->last_height = -1;
}
static void vga_reset(VGAState *s)
static void vga_reset(void *opaque)
{
memset(s, 0, sizeof(VGAState));
VGAState *s = (VGAState *) opaque;
s->lfb_addr = 0;
s->lfb_end = 0;
s->map_addr = 0;
s->map_end = 0;
s->lfb_vram_mapped = 0;
s->bios_offset = 0;
s->bios_size = 0;
s->sr_index = 0;
memset(s->sr, '\0', sizeof(s->sr));
s->gr_index = 0;
memset(s->gr, '\0', sizeof(s->gr));
s->ar_index = 0;
memset(s->ar, '\0', sizeof(s->ar));
s->ar_flip_flop = 0;
s->cr_index = 0;
memset(s->cr, '\0', sizeof(s->cr));
s->msr = 0;
s->fcr = 0;
s->st00 = 0;
s->st01 = 0;
s->dac_state = 0;
s->dac_sub_index = 0;
s->dac_read_index = 0;
s->dac_write_index = 0;
memset(s->dac_cache, '\0', sizeof(s->dac_cache));
s->dac_8bit = 0;
memset(s->palette, '\0', sizeof(s->palette));
s->bank_offset = 0;
#ifdef CONFIG_BOCHS_VBE
s->vbe_index = 0;
memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
s->vbe_start_addr = 0;
s->vbe_line_offset = 0;
s->vbe_bank_mask = (s->vram_size >> 16) - 1;
#endif
memset(s->font_offsets, '\0', sizeof(s->font_offsets));
s->graphic_mode = -1; /* force full update */
s->shift_control = 0;
s->double_scan = 0;
s->line_offset = 0;
s->line_compare = 0;
s->start_addr = 0;
s->plane_updated = 0;
s->last_cw = 0;
s->last_ch = 0;
s->last_width = 0;
s->last_height = 0;
s->last_scr_width = 0;
s->last_scr_height = 0;
s->cursor_start = 0;
s->cursor_end = 0;
s->cursor_offset = 0;
memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
memset(s->last_palette, '\0', sizeof(s->last_palette));
memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
switch (vga_retrace_method) {
case VGA_RETRACE_DUMB:
break;
case VGA_RETRACE_PRECISE:
memset(&s->retrace_info, 0, sizeof (s->retrace_info));
break;
}
}
#define TEXTMODE_X(x) ((x) % width)
@ -2179,8 +2242,6 @@ void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
expand4to8[i] = v;
}
vga_reset(s);
s->vram_ptr = vga_ram_base;
s->vram_offset = vga_ram_offset;
s->vram_size = vga_ram_size;
@ -2201,9 +2262,10 @@ void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
case VGA_RETRACE_PRECISE:
s->retrace = vga_precise_retrace;
s->update_retrace_info = vga_precise_update_retrace_info;
memset(&s->retrace_info, 0, sizeof (s->retrace_info));
break;
}
qemu_register_reset(vga_reset, s);
vga_reset(s);
}
/* used by both ISA and PCI */
@ -2229,8 +2291,6 @@ void vga_init(VGAState *s)
s->bank_offset = 0;
#ifdef CONFIG_BOCHS_VBE
s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
#if defined (TARGET_I386)
register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);