Sparc32: move intbit_to_level table back to slavio_intctl.c
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
4b48bf059b
commit
68556e2e9e
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@ -67,7 +67,6 @@ typedef struct SLAVIO_INTCTLState {
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uint64_t irq_count[32];
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#endif
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qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
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const uint32_t *intbit_to_level;
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uint32_t cputimer_lbit, cputimer_mbit;
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uint32_t cputimer_bit;
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uint32_t pil_out[MAX_CPUS];
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@ -252,6 +251,11 @@ void slavio_irq_info(Monitor *mon, void *opaque)
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#endif
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}
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static const uint32_t intbit_to_level[] = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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};
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static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
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{
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uint32_t pending = s->intregm_pending, pil_pending;
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@ -266,7 +270,7 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
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(i == s->target_cpu)) {
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for (j = 0; j < 32; j++) {
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if (pending & (1 << j))
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pil_pending |= 1 << s->intbit_to_level[j];
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pil_pending |= 1 << intbit_to_level[j];
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}
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}
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pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
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@ -296,7 +300,7 @@ static void slavio_set_irq(void *opaque, int irq, int level)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t mask = 1 << irq;
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uint32_t pil = s->intbit_to_level[irq];
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uint32_t pil = intbit_to_level[irq];
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DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
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level);
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@ -397,7 +401,7 @@ static void slavio_intctl_init1(SysBusDevice *dev)
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slavio_intctlm_mem_write, s);
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sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
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s->cputimer_mbit = 1 << s->cputimer_bit;
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s->cputimer_lbit = 1 << s->intbit_to_level[s->cputimer_bit];
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s->cputimer_lbit = 1 << intbit_to_level[s->cputimer_bit];
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for (i = 0; i < MAX_CPUS; i++) {
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for (j = 0; j < MAX_PILS; j++) {
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@ -421,11 +425,6 @@ static SysBusDeviceInfo slavio_intctl_info = {
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.qdev.name = "slavio_intctl",
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.qdev.size = sizeof(SLAVIO_INTCTLState),
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.qdev.props = (Property[]) {
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{
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.name = "intbit_to_level",
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.info = &qdev_prop_ptr,
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.offset = offsetof(SLAVIO_INTCTLState, intbit_to_level),
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},
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{
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.name = "cputimer_bit",
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.info = &qdev_prop_uint32,
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41
hw/sun4m.c
41
hw/sun4m.c
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@ -105,7 +105,6 @@ struct sun4m_hwdef {
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uint8_t nvram_machine_id;
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uint16_t machine_id;
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uint32_t iommu_version;
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uint32_t intbit_to_level[32];
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uint64_t max_mem;
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const char * const default_cpu_model;
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};
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@ -145,7 +144,6 @@ struct sun4c_hwdef {
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uint8_t nvram_machine_id;
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uint16_t machine_id;
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uint32_t iommu_version;
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uint32_t intbit_to_level[32];
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uint64_t max_mem;
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const char * const default_cpu_model;
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};
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@ -400,7 +398,6 @@ static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
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static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
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target_phys_addr_t addrg,
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const uint32_t *intbit_to_level,
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qemu_irq **parent_irq,
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unsigned int cputimer)
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{
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@ -409,7 +406,6 @@ static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
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unsigned int i, j;
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dev = qdev_create(NULL, "slavio_intctl");
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qdev_prop_set_ptr(dev, "intbit_to_level", (void *)intbit_to_level);
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qdev_prop_set_uint32(dev, "cputimer_bit", cputimer);
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qdev_init(dev);
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@ -781,7 +777,6 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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dev = slavio_intctl_init(hwdef->intctl_base,
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hwdef->intctl_base + 0x10000ULL,
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&hwdef->intbit_to_level[0],
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cpu_irqs,
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hwdef->clock_irq);
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@ -941,10 +936,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x80,
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.machine_id = ss5_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "Fujitsu MB86904",
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},
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@ -982,10 +973,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x72,
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.machine_id = ss10_id,
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.iommu_version = 0x03000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0xf00000000ULL,
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.default_cpu_model = "TI SuperSparc II",
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},
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@ -1021,10 +1008,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x71,
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.machine_id = ss600mp_id,
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.iommu_version = 0x01000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0xf00000000ULL,
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.default_cpu_model = "TI SuperSparc II",
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},
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@ -1062,10 +1045,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x72,
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.machine_id = ss20_id,
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.iommu_version = 0x13000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0xf00000000ULL,
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.default_cpu_model = "TI SuperSparc II",
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},
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@ -1100,10 +1079,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x80,
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.machine_id = vger_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "Fujitsu MB86904",
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},
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@ -1137,10 +1112,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x80,
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.machine_id = lx_id,
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.iommu_version = 0x04000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "TI MicroSparc I",
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},
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@ -1177,10 +1148,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x80,
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.machine_id = ss4_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "Fujitsu MB86904",
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},
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@ -1215,10 +1182,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x80,
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.machine_id = scls_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "TI MicroSparc I",
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},
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@ -1253,10 +1216,6 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.nvram_machine_id = 0x80,
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.machine_id = sbook_id,
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.iommu_version = 0x05000000,
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.intbit_to_level = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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},
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.max_mem = 0x10000000,
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.default_cpu_model = "TI MicroSparc I",
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},
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