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Implement basic part of SA-1110/SA-1100 

Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.
Implemented:
 - IRQs
 - GPIO
 - PPC
 - RTC
 - UARTs (no IrDA/etc.)
 - OST reused from pxa25x

Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the
hw/strongarm.c

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Dmitry Eremin-Solenikov 2011-04-19 18:56:45 +04:00 committed by Aurelien Jarno
parent 618ba8e6a1
commit 5bc95aa246
5 changed files with 1675 additions and 0 deletions
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1
Makefile.target
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@ -352,6 +352,7 @@ obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
obj-arm-y += syborg_virtio.o
obj-arm-y += vexpress.o
obj-arm-y += strongarm.o
obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o

1598
hw/strongarm.c Normal file
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File diff suppressed because it is too large Load Diff

64
hw/strongarm.h Normal file
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@ -0,0 +1,64 @@
#ifndef _STRONGARM_H
#define _STRONGARM_H
#define SA_CS0 0x00000000
#define SA_CS1 0x08000000
#define SA_CS2 0x10000000
#define SA_CS3 0x18000000
#define SA_PCMCIA_CS0 0x20000000
#define SA_PCMCIA_CS1 0x30000000
#define SA_CS4 0x40000000
#define SA_CS5 0x48000000
/* system registers here */
#define SA_SDCS0 0xc0000000
#define SA_SDCS1 0xc8000000
#define SA_SDCS2 0xd0000000
#define SA_SDCS3 0xd8000000
enum {
SA_PIC_GPIO0_EDGE = 0,
SA_PIC_GPIO1_EDGE,
SA_PIC_GPIO2_EDGE,
SA_PIC_GPIO3_EDGE,
SA_PIC_GPIO4_EDGE,
SA_PIC_GPIO5_EDGE,
SA_PIC_GPIO6_EDGE,
SA_PIC_GPIO7_EDGE,
SA_PIC_GPIO8_EDGE,
SA_PIC_GPIO9_EDGE,
SA_PIC_GPIO10_EDGE,
SA_PIC_GPIOX_EDGE,
SA_PIC_LCD,
SA_PIC_UDC,
SA_PIC_RSVD1,
SA_PIC_UART1,
SA_PIC_UART2,
SA_PIC_UART3,
SA_PIC_MCP,
SA_PIC_SSP,
SA_PIC_DMA_CH0,
SA_PIC_DMA_CH1,
SA_PIC_DMA_CH2,
SA_PIC_DMA_CH3,
SA_PIC_DMA_CH4,
SA_PIC_DMA_CH5,
SA_PIC_OSTC0,
SA_PIC_OSTC1,
SA_PIC_OSTC2,
SA_PIC_OSTC3,
SA_PIC_RTC_HZ,
SA_PIC_RTC_ALARM,
};
typedef struct {
CPUState *env;
DeviceState *pic;
DeviceState *gpio;
DeviceState *ppc;
DeviceState *ssp;
SSIBus *ssp_bus;
} StrongARMState;
StrongARMState *sa1110_init(unsigned int sdram_size, const char *rev);
#endif

3
target-arm/cpu.h
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@ -363,6 +363,7 @@ enum arm_features {
ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
ARM_FEATURE_V4T,
ARM_FEATURE_V5,
ARM_FEATURE_STRONGARM,
};
static inline int arm_feature(CPUARMState *env, int feature)
@ -393,6 +394,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_ARM946 0x41059461
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
#define ARM_CPUID_SA1100 0x4401A11B
#define ARM_CPUID_SA1110 0x6901B119
#define ARM_CPUID_PXA250 0x69052100
#define ARM_CPUID_PXA255 0x69052d00
#define ARM_CPUID_PXA260 0x69052903

9
target-arm/helper.c
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@ -214,6 +214,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110:
set_feature(env, ARM_FEATURE_STRONGARM);
env->cp15.c1_sys = 0x00000070;
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
break;
@ -378,6 +383,8 @@ static const struct arm_cpu_t arm_cpu_names[] = {
{ ARM_CPUID_CORTEXA9, "cortex-a9"},
{ ARM_CPUID_TI925T, "ti925t" },
{ ARM_CPUID_PXA250, "pxa250" },
{ ARM_CPUID_SA1100, "sa1100" },
{ ARM_CPUID_SA1110, "sa1110" },
{ ARM_CPUID_PXA255, "pxa255" },
{ ARM_CPUID_PXA260, "pxa260" },
{ ARM_CPUID_PXA261, "pxa261" },
@ -1553,6 +1560,8 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
case 9:
if (arm_feature(env, ARM_FEATURE_OMAPCP))
break;
if (arm_feature(env, ARM_FEATURE_STRONGARM))
break; /* Ignore ReadBuffer access */
switch (crm) {
case 0: /* Cache lockdown. */
switch (op1) {