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MIPS: Initial support of fulong mini pc (CPU definition) 

Signed-off-by: Huacai Chen <zltjiangshi@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Huacai Chen 2010-06-29 10:50:27 +08:00 committed by Aurelien Jarno
parent 30235a54dc
commit 5bc6fba851
2 changed files with 39 additions and 0 deletions
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4
target-mips/mips-defs.h
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@ -41,6 +41,8 @@
#define ASE_MICROMIPS 0x00080000
/* Chip specific instructions. */
#define INSN_LOONGSON2E 0x20000000
#define INSN_LOONGSON2F 0x40000000
#define INSN_VR54XX 0x80000000
/* MIPS CPU defines. */
@ -49,6 +51,8 @@
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)

35
target-mips/translate_init.c
View File

@ -454,6 +454,41 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "Loongson-2E",
.CP0_PRid = 0x6302,
/*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
.CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
(0x1<<4) | (0x1<<1),
/* Note: Config1 is only used internally, Loongson-2E has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.SYNCI_Step = 16,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x35D0FFFF,
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
.SEGBITS = 40,
.PABITS = 40,
.insn_flags = CPU_LOONGSON2E,
.mmu_type = MMU_TYPE_R4000,
},
{
.name = "Loongson-2F",
.CP0_PRid = 0x6303,
/*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
.CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
(0x1<<4) | (0x1<<1),
/* Note: Config1 is only used internally, Loongson-2F has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.SYNCI_Step = 16,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
.SEGBITS = 40,
.PABITS = 40,
.insn_flags = CPU_LOONGSON2F,
.mmu_type = MMU_TYPE_R4000,
},
#endif
};