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SPARC: Add asr17 register support 

This register is activated by CPU_FEATURE_ASR17 in the feature field.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Fabien Chouteau 2011-01-24 12:56:56 +01:00 committed by Blue Swirl
parent b04d989054
commit 4a2ba23284
3 changed files with 14 additions and 1 deletions
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1
target-sparc/cpu.h
View File

@ -267,6 +267,7 @@ typedef struct sparc_def_t {
#define CPU_FEATURE_CMT (1 << 12)
#define CPU_FEATURE_GL (1 << 13)
#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
#define CPU_FEATURE_ASR17 (1 << 15)
#ifndef TARGET_SPARC64
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
CPU_FEATURE_MUL | CPU_FEATURE_DIV | \

3
target-sparc/helper.c
View File

@ -1288,7 +1288,8 @@ static const sparc_def_t sparc_defs[] = {
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
CPU_FEATURE_ASR17,
},
#endif
};

11
target-sparc/translate.c
View File

@ -2067,6 +2067,17 @@ static void disas_sparc_insn(DisasContext * dc)
case 0x10 ... 0x1f: /* implementation-dependent in the
SPARCv8 manual, rdy on the
microSPARC II */
/* Read Asr17 */
if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
TCGv r_const;
/* Read Asr17 for a Leon3 monoprocessor */
r_const = tcg_const_tl((1 << 8)
| (dc->def->nwindows - 1));
gen_movl_TN_reg(rd, r_const);
tcg_temp_free(r_const);
break;
}
#endif
gen_movl_TN_reg(rd, cpu_y);
break;