Code provision for new PowerPC embedded target support with:

- 1 kB page size - 64 bits GPR - 64 bits physical address space - SPE extension support. Change TARGET_PPCSPE into TARGET_PPCEMB git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2718 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-24 06:50:21 +00:00 · 2007-04-24 06:50:21 +00:00 · 35cdaad645
parent c294fc587a
commit 35cdaad645
8 changed files with 26 additions and 21 deletions
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@ -23,11 +23,13 @@
 #include "config.h"
 #include <inttypes.h>

+#if !defined(TARGET_PPCEMB)
 #if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)
 /* When using 64 bits temporary registers,
 * we can use 64 bits GPR with no extra cost
 */
-#define TARGET_PPCSPE
+#define TARGET_PPCEMB
+#endif
 #endif

 #if defined (TARGET_PPC64)
@ -35,7 +37,8 @@ typedef uint64_t ppc_gpr_t;
 #define TARGET_LONG_BITS 64
 #define TARGET_GPR_BITS  64
 #define REGX "%016" PRIx64
-#elif defined(TARGET_PPCSPE)
+#define TARGET_PAGE_BITS 12
+#elif defined(TARGET_PPCEMB)
 /* e500v2 have 36 bits physical address space */
 #define TARGET_PHYS_ADDR_BITS 64
 /* GPR are 64 bits: used by vector extension */
@ -43,11 +46,14 @@ typedef uint64_t ppc_gpr_t;
 #define TARGET_LONG_BITS 32
 #define TARGET_GPR_BITS  64
 #define REGX "%016" PRIx64
+/* Pages can be 1 kB small */
+#define TARGET_PAGE_BITS 10
 #else
 typedef uint32_t ppc_gpr_t;
 #define TARGET_LONG_BITS 32
 #define TARGET_GPR_BITS  32
 #define REGX "%08" PRIx32
+#define TARGET_PAGE_BITS 12
 #endif

 #include "cpu-defs.h"
@ -893,7 +899,6 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address);
 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);

-#define TARGET_PAGE_BITS 12
 #include "cpu-all.h"

 /*****************************************************************************/
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@ -43,7 +43,7 @@ register unsigned long T1 asm(AREG2);
 register unsigned long T2 asm(AREG3);
 #endif
 /* We may, sometime, need 64 bits registers on 32 bits target */
-#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE) || (HOST_LONG_BITS == 64)
+#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB) || (HOST_LONG_BITS == 64)
 #define T0_64 T0
 #define T1_64 T1
 #define T2_64 T2
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@ -2479,7 +2479,7 @@ void OPPROTO op_store_booke_tsr (void)

 #endif /* !defined(CONFIG_USER_ONLY) */

-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
 /* SPE extension */
 void OPPROTO op_splatw_T1_64 (void)
 {
@ -3198,4 +3198,4 @@ void OPPROTO op_efdtsteq (void)
    T0 = _do_efdtsteq(T0_64, T1_64);
    RETURN();
 }
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@ -1340,7 +1340,7 @@ void do_440_dlmzb (void)
    T0 = i;
 }

-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
 /* SPE extension helpers */
 /* Use a table to make this quicker */
 static uint8_t hbrev[16] = {
@ -2200,7 +2200,7 @@ DO_SPE_OP1(fsctuiz);
 DO_SPE_OP1(fsctsf);
 /* evfsctuf */
 DO_SPE_OP1(fsctuf);
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */

 /*****************************************************************************/
 /* Softmmu support */
--- a/target-ppc/op_helper.h
+++ b/target-ppc/op_helper.h
@ -183,7 +183,7 @@ void do_load_403_pb (int num);
 void do_store_403_pb (int num);
 #endif

-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
 /* SPE extension helpers */
 void do_brinc (void);
 /* Fixed-point vector helpers */
@ -264,7 +264,7 @@ void do_evfsctsi (void);
 void do_evfsctui (void);
 void do_evfsctsiz (void);
 void do_evfsctuiz (void);
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */

 /* Inlined helpers: used in micro-operation as well as helpers */
 /* Generic fixed-point helpers */
@ -338,7 +338,7 @@ static inline int _do_cntlzd (uint64_t val)
    return cnt;
 }

-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
 /* SPE extension */
 /* Single precision floating-point helpers */
 static inline uint32_t _do_efsabs (uint32_t val)
@ -459,5 +459,5 @@ static inline int _do_efdtsteq (uint64_t op1, uint64_t op2)
    u2.u = op2;
    return float64_eq(u1.f, u2.f, &env->spe_status) ? 1 : 0;
 }
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */
 #endif
--- a/target-ppc/op_mem.h
+++ b/target-ppc/op_mem.h
@ -37,7 +37,7 @@ static inline uint32_t glue(ld32r, MEMSUFFIX) (target_ulong EA)
        ((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
 }

-#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE)
+#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB)
 static inline uint64_t glue(ld64r, MEMSUFFIX) (target_ulong EA)
 {
    uint64_t tmp = glue(ldq, MEMSUFFIX)(EA);
@ -79,7 +79,7 @@ static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, uint32_t data)
    glue(stl, MEMSUFFIX)(EA, tmp);
 }

-#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE)
+#if defined(TARGET_PPC64) || defined(TARGET_PPCEMB)
 static inline void glue(st64r, MEMSUFFIX) (target_ulong EA, uint64_t data)
 {
    uint64_t tmp = ((data & 0xFF00000000000000ULL) >> 56) |
@ -895,7 +895,7 @@ void OPPROTO glue(op_POWER2_stfq_le, MEMSUFFIX) (void)
    RETURN();
 }

-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
 /* SPE extension */
 #define _PPC_SPE_LD_OP(name, op)                                              \
 void OPPROTO glue(glue(op_spe_l, name), MEMSUFFIX) (void)                     \
@ -1151,6 +1151,6 @@ static inline uint64_t glue(spe_lwhsplat_le, MEMSUFFIX) (target_ulong EA)
    return ret;
 }
 PPC_SPE_LD_OP(whsplat_le, spe_lwhsplat_le);
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */

 #undef MEMSUFFIX
--- a/target-ppc/op_template.h
+++ b/target-ppc/op_template.h
@ -57,7 +57,7 @@ void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
 }
 #endif

-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
 void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
 {
    T0_64 = regs->gpr[REG];
@ -97,7 +97,7 @@ void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
    RETURN();
 }
 #endif
-#endif /* defined(TARGET_PPCSPE) */
+#endif /* defined(TARGET_PPCEMB) */

 #if REG <= 7
 /* Condition register moves */
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@ -161,7 +161,7 @@ typedef struct DisasContext {
    int sf_mode;
 #endif
    int fpu_enabled;
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
    int spe_enabled;
 #endif
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
@ -4761,7 +4761,7 @@ GEN_HANDLER(icbt_440, 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
     */
 }

-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
 /***                           SPE extension                               ***/

 /* Register moves */
@ -5740,7 +5740,7 @@ static inline int gen_intermediate_code_internal (CPUState *env,
    ctx.sf_mode = msr_sf;
 #endif
    ctx.fpu_enabled = msr_fp;
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
    ctx.spe_enabled = msr_spe;
 #endif
    ctx.singlestep_enabled = env->singlestep_enabled;