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fix alpha cmovxx instruction 

The CMOV instruction is defined by the alpha manual as:

CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format
CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format

Operation:
IF TEST(Rav, Condition_based_on_Opcode) THEN
Rc ← Rbv

The current qemu behavior inverses Ra and Rb.  This is fixed by this
patch.

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-09-05 19:07:53 +00:00
parent 980f8a0b39
commit 29d26d20e5
1 changed files with 7 additions and 7 deletions
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14
target-alpha/translate.c
View File

@ -390,15 +390,15 @@ static always_inline void gen_cmov (DisasContext *ctx,
int islit, int8_t lit)
{
if (ra != 31)
tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
else
tcg_gen_movi_i64(cpu_T[1], 0);
if (islit)
tcg_gen_movi_i64(cpu_T[0], lit);
else if (rb != 31)
tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
else
tcg_gen_movi_i64(cpu_T[0], 0);
if (islit)
tcg_gen_movi_i64(cpu_T[1], lit);
else if (rb != 31)
tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
else
tcg_gen_movi_i64(cpu_T[1], 0);
(*gen_test_op)();
gen_op_cmov_ir(rc);
}