sim-card
/
qemu
Archived
10
0
Fork 0
Code Releases Activity

Convert array8/16/32 and alignaddr to TCG 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4085 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-03-18 18:06:54 +00:00
parent eb24dadde5
commit 1f5063fb97
4 changed files with 45 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target-sparc/helper.h
View File

@ -8,6 +8,10 @@ target_ulong TCG_HELPER_PROTO helper_rdpsr(void);
void TCG_HELPER_PROTO helper_wrpstate(target_ulong new_state);
void TCG_HELPER_PROTO helper_done(void);
void TCG_HELPER_PROTO helper_retry(void);
target_ulong TCG_HELPER_PROTO helper_array8(target_ulong pixel_addr,
target_ulong cubesize);
target_ulong TCG_HELPER_PROTO helper_alignaddr(target_ulong addr,
target_ulong offset);
target_ulong TCG_HELPER_PROTO helper_popc(target_ulong val);
void TCG_HELPER_PROTO helper_ldf_asi(target_ulong addr, int asi, int size,
int rd);

48
target-sparc/op.c
View File

@ -568,54 +568,6 @@ void OPPROTO op_restored(void)
#endif
#ifdef TARGET_SPARC64
// This function uses non-native bit order
#define GET_FIELD(X, FROM, TO) \
((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
// This function uses the order in the manuals, i.e. bit 0 is 2^0
#define GET_FIELD_SP(X, FROM, TO) \
GET_FIELD(X, 63 - (TO), 63 - (FROM))
void OPPROTO op_array8()
{
T0 = (GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
(GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
(GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
(GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
(GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
(GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12);
}
void OPPROTO op_array16()
{
T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
(GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
(GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
(GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
(GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
(GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 1;
}
void OPPROTO op_array32()
{
T0 = ((GET_FIELD_SP(T0, 60, 63) << (17 + 2 * T1)) |
(GET_FIELD_SP(T0, 39, 39 + T1 - 1) << (17 + T1)) |
(GET_FIELD_SP(T0, 17 + T1 - 1, 17) << 17) |
(GET_FIELD_SP(T0, 56, 59) << 13) | (GET_FIELD_SP(T0, 35, 38) << 9) |
(GET_FIELD_SP(T0, 13, 16) << 5) | (((T0 >> 55) & 1) << 4) |
(GET_FIELD_SP(T0, 33, 34) << 2) | GET_FIELD_SP(T0, 11, 12)) << 2;
}
void OPPROTO op_alignaddr()
{
uint64_t tmp;
tmp = T0 + T1;
env->gsr &= ~7ULL;
env->gsr |= tmp & 7ULL;
T0 = tmp & ~7ULL;
}
void OPPROTO op_faligndata()
{
uint64_t tmp;

31
target-sparc/op_helper.c
View File

@ -1637,6 +1637,37 @@ target_ulong helper_rdpsr(void)
#else
// This function uses non-native bit order
#define GET_FIELD(X, FROM, TO) \
((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
// This function uses the order in the manuals, i.e. bit 0 is 2^0
#define GET_FIELD_SP(X, FROM, TO) \
GET_FIELD(X, 63 - (TO), 63 - (FROM))
target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
{
return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
(GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
(GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
(GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
(GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
(GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
(((pixel_addr >> 55) & 1) << 4) |
(GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
GET_FIELD_SP(pixel_addr, 11, 12);
}
target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
{
uint64_t tmp;
tmp = addr + offset;
env->gsr &= ~7ULL;
env->gsr |= tmp & 7ULL;
return tmp & ~7ULL;
}
target_ulong helper_popc(target_ulong val)
{
return ctpop64(val);

14
target-sparc/translate.c
View File

@ -3515,25 +3515,31 @@ static void disas_sparc_insn(DisasContext * dc)
case 0x010: /* VIS I array8 */
gen_movl_reg_T0(rs1);
gen_movl_reg_T1(rs2);
gen_op_array8();
tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
cpu_T[1]);
gen_movl_T0_reg(rd);
break;
case 0x012: /* VIS I array16 */
gen_movl_reg_T0(rs1);
gen_movl_reg_T1(rs2);
gen_op_array16();
tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
cpu_T[1]);
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1);
gen_movl_T0_reg(rd);
break;
case 0x014: /* VIS I array32 */
gen_movl_reg_T0(rs1);
gen_movl_reg_T1(rs2);
gen_op_array32();
tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0],
cpu_T[1]);
tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
gen_movl_T0_reg(rd);
break;
case 0x018: /* VIS I alignaddr */
gen_movl_reg_T0(rs1);
gen_movl_reg_T1(rs2);
gen_op_alignaddr();
tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0],
cpu_T[1]);
gen_movl_T0_reg(rd);
break;
case 0x019: /* VIS II bmask */