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Remove io_index argument from cpu_register_io_memory() 

The parameter is always zero except when registering the three internal
io regions (ROM, unassigned, notdirty).  Remove the parameter to reduce
the API's power, thus facilitating future change.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2009-06-14 11:38:51 +03:00 committed by Anthony Liguori
parent dff840348e
commit 1eed09cb4a
140 changed files with 291 additions and 283 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
cpu-common.h
View File

@ -41,8 +41,7 @@ void *qemu_get_ram_ptr(ram_addr_t addr);
/* This should not be used by devices. */
ram_addr_t qemu_ram_addr_from_host(void *ptr);
int cpu_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read,
int cpu_register_io_memory(CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write,
void *opaque);
void cpu_unregister_io_memory(int table_address);

31
exec.c
View File

@ -3004,7 +3004,7 @@ static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
mmio = qemu_mallocz(sizeof(subpage_t));
mmio->base = base;
subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
#if defined(DEBUG_SUBPAGE)
printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
@ -3029,17 +3029,22 @@ static int get_free_io_mem_idx(void)
return -1;
}
static int cpu_register_io_memory_fixed(int io_index,
CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write,
void *opaque);
static void io_mem_init(void)
{
int i;
cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL);
cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL);
cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL);
for (i=0; i<5; i++)
io_mem_used[i] = 1;
io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
io_mem_watch = cpu_register_io_memory(watch_mem_read,
watch_mem_write, NULL);
#ifdef CONFIG_KQEMU
if (kqemu_phys_ram_base) {
@ -3057,10 +3062,10 @@ static void io_mem_init(void)
modified. If it is zero, a new io zone is allocated. The return
value can be used with cpu_register_physical_memory(). (-1) is
returned if error. */
int cpu_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write,
void *opaque)
static int cpu_register_io_memory_fixed(int io_index,
CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write,
void *opaque)
{
int i, subwidth = 0;
@ -3069,6 +3074,7 @@ int cpu_register_io_memory(int io_index,
if (io_index == -1)
return io_index;
} else {
io_index >>= IO_MEM_SHIFT;
if (io_index >= IO_MEM_NB_ENTRIES)
return -1;
}
@ -3083,6 +3089,13 @@ int cpu_register_io_memory(int io_index,
return (io_index << IO_MEM_SHIFT) | subwidth;
}
int cpu_register_io_memory(CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write,
void *opaque)
{
return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
}
void cpu_unregister_io_memory(int io_table_address)
{
int i;

8
hw/apb_pci.c
View File

@ -234,13 +234,13 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
s->bus = pci_register_bus(NULL, "pci",
pci_apb_set_irq, pci_pbm_map_irq, pic, 0, 32);
pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
pci_mem_config = cpu_register_io_memory(pci_apb_config_read,
pci_apb_config_write, s);
apb_config = cpu_register_io_memory(0, apb_config_read,
apb_config = cpu_register_io_memory(apb_config_read,
apb_config_write, s);
pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
pci_mem_data = cpu_register_io_memory(pci_apb_read,
pci_apb_write, s);
pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
pci_ioport = cpu_register_io_memory(pci_apb_ioread,
pci_apb_iowrite, s);
cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config);

2
hw/apic.c
View File

@ -936,7 +936,7 @@ int apic_init(CPUState *env)
if (apic_io_memory == 0) {
/* NOTE: the APIC is directly connected to the CPU - it is not
on the global memory bus. */
apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
apic_io_memory = cpu_register_io_memory(apic_mem_read,
apic_mem_write, NULL);
cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
apic_io_memory);

2
hw/arm_gic.c
View File

@ -725,7 +725,7 @@ static void gic_init(gic_state *s)
for (i = 0; i < NCPU; i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
s->iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
gic_dist_writefn, s);
gic_reset(s);
register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);

2
hw/arm_sysctl.c
View File

@ -198,7 +198,7 @@ static void arm_sysctl_init1(SysBusDevice *dev)
/* The MPcore bootloader uses these flags to start secondary CPUs.
We don't use a bootloader, so do this here. */
s->flags = 3;
iomemtype = cpu_register_io_memory(0, arm_sysctl_readfn,
iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
arm_sysctl_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* ??? Save/restore. */

4
hw/arm_timer.c
View File

@ -268,7 +268,7 @@ static void sp804_init(SysBusDevice *dev)
s->timer[1] = arm_timer_init(1000000);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
iomemtype = cpu_register_io_memory(0, sp804_readfn,
iomemtype = cpu_register_io_memory(sp804_readfn,
sp804_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
@ -338,7 +338,7 @@ static void icp_pit_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->timer[1]->irq);
sysbus_init_irq(dev, &s->timer[2]->irq);
iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
iomemtype = cpu_register_io_memory(icp_pit_readfn,
icp_pit_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* This device has no state to save/restore. The component timers will

2
hw/armv7m.c
View File

@ -128,7 +128,7 @@ static void bitband_init(SysBusDevice *dev)
int iomemtype;
s->base = qdev_get_prop_int(&dev->qdev, "base", 0);
iomemtype = cpu_register_io_memory(0, bitband_readfn, bitband_writefn,
iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
&s->base);
sysbus_init_mmio(dev, 0x02000000, iomemtype);
}

4
hw/axis_dev88.c
View File

@ -286,11 +286,11 @@ void axisdev88_init (ram_addr_t ram_size,
/* Attach a NAND flash to CS1. */
nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
nand_regs = cpu_register_io_memory(0, nand_read, nand_write, &nand_state);
nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state);
cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
gpio_state.nand = &nand_state;
gpio_regs = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state);
gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state);
cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);

8
hw/cirrus_vga.c
View File

@ -3196,7 +3196,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
s->vga.vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
cirrus_vga_mem_write, s);
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
s->vga.vga_io_memory);
@ -3204,16 +3204,16 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
/* I/O handler for LFB */
s->cirrus_linear_io_addr =
cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s);
cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s);
/* I/O handler for LFB */
s->cirrus_linear_bitblt_io_addr =
cpu_register_io_memory(0, cirrus_linear_bitblt_read,
cpu_register_io_memory(cirrus_linear_bitblt_read,
cirrus_linear_bitblt_write, s);
/* I/O handler for memory-mapped I/O */
s->cirrus_mmio_io_addr =
cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s);
s->real_vram_size =
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;

2
hw/cs4231.c
View File

@ -172,7 +172,7 @@ void cs_init(target_phys_addr_t base, int irq, void *intctl)
s = qemu_mallocz(sizeof(CSState));
cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
cs_io_memory = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);
cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);
register_savevm("cs4231", base, 1, cs_save, cs_load, s);
qemu_register_reset(cs_reset, 0, s);

2
hw/cuda.c
View File

@ -760,7 +760,7 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);
register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);
qemu_register_reset(cuda_reset, 0, s);
cuda_reset(s);

2
hw/dp8393x.c
View File

@ -897,6 +897,6 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_register_reset(nic_reset, 0, s);
nic_reset(s);
s->mmio_index = cpu_register_io_memory(0, dp8393x_read, dp8393x_write, s);
s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
}

4
hw/ds1225y.c
View File

@ -171,10 +171,10 @@ void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
}
/* Read/write memory */
mem_indexRW = cpu_register_io_memory(0, nvram_read, nvram_write, s);
mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s);
cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
/* Read/write protected memory */
mem_indexRP = cpu_register_io_memory(0, nvram_read, nvram_write_protected, s);
mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s);
cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP);
return s;
}

2
hw/e1000.c
View File

@ -1101,7 +1101,7 @@ static void pci_e1000_init(PCIDevice *pci_dev)
pci_conf[0x3d] = 1; // interrupt pin 0
d->mmio_index = cpu_register_io_memory(0, e1000_mmio_read,
d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
e1000_mmio_write, d);
pci_register_io_region((PCIDevice *)d, 0, PNPMMIO_SIZE,

4
hw/eccmemctl.c
View File

@ -325,10 +325,10 @@ void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
s->regs[0] = version;
s->irq = irq;
ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s);
cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
if (version == ECC_MCC) { // SS-600MP only
ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
ecc_diag_mem_write, s);
cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
ecc_io_memory);

2
hw/eepro100.c
View File

@ -1750,7 +1750,7 @@ static void nic_init(PCIDevice *pci_dev, uint32_t device)
/* Handler for memory-mapped I/O */
d->eepro100.mmio_index =
cpu_register_io_memory(0, pci_mmio_read, pci_mmio_write, s);
cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
pci_register_io_region(&d->dev, 0, PCI_MEM_SIZE,
PCI_ADDRESS_SPACE_MEM |

4
hw/escc.c
View File

@ -728,7 +728,7 @@ int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
s = qemu_mallocz(sizeof(SerialState));
escc_io_memory = cpu_register_io_memory(0, escc_mem_read,
escc_io_memory = cpu_register_io_memory(escc_mem_read,
escc_mem_write,
s);
if (base)
@ -922,7 +922,7 @@ void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
s->chn[0].disabled = disabled;
s->chn[1].disabled = disabled;
slavio_serial_io_memory = cpu_register_io_memory(0, escc_mem_read,
slavio_serial_io_memory = cpu_register_io_memory(escc_mem_read,
escc_mem_write,
s);
cpu_register_physical_memory(base, ESCC_SIZE << it_shift,

2
hw/esp.c
View File

@ -676,7 +676,7 @@ static void esp_init1(SysBusDevice *dev)
s->dma_memory_write = qdev_get_prop_ptr(&dev->qdev, "dma_memory_write");
s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma_opaque");
esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
esp_reset(s);

2
hw/etraxfs_dma.c
View File

@ -750,7 +750,7 @@ void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
ctrl->nr_channels = nr_channels;
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
ctrl->map = cpu_register_io_memory(0, dma_read, dma_write, ctrl);
ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl);
cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
return ctrl;
}

2
hw/etraxfs_eth.c
View File

@ -587,7 +587,7 @@ void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
tdk_init(&eth->phy);
mdio_attach(&eth->mdio_bus, &eth->phy, eth->phyaddr);
eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth);
eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth);
cpu_register_physical_memory (base, 0x5c, eth->ethregs);
eth->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,

2
hw/etraxfs_pic.c
View File

@ -145,7 +145,7 @@ static void etraxfs_pic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_nmi);
intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, s);
intr_vect_regs = cpu_register_io_memory(pic_read, pic_write, s);
sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs);
}

2
hw/etraxfs_ser.c
View File

@ -171,7 +171,7 @@ static void etraxfs_ser_init(SysBusDevice *dev)
s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
sysbus_init_irq(dev, &s->irq);
ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
ser_regs = cpu_register_io_memory(ser_read, ser_write, s);
sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr)

2
hw/etraxfs_timer.c
View File

@ -323,7 +323,7 @@ static void etraxfs_timer_init(SysBusDevice *dev)
sysbus_init_irq(dev, &t->irq);
sysbus_init_irq(dev, &t->nmi);
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
sysbus_init_mmio(dev, 0x5c, timer_regs);
qemu_register_reset(etraxfs_timer_reset, 0, t);

4
hw/fdc.c
View File

@ -1902,7 +1902,7 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
fdctrl->sun4m = 0;
if (mem_mapped) {
io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
io_mem = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write,
fdctrl);
cpu_register_physical_memory(io_base, 0x08, io_mem);
} else {
@ -1927,7 +1927,7 @@ fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
fdctrl = fdctrl_init_common(irq, -1, io_base, fds);
fdctrl->sun4m = 1;
io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
io_mem = cpu_register_io_memory(fdctrl_mem_read_strict,
fdctrl_mem_write_strict,
fdctrl);
cpu_register_physical_memory(io_base, 0x08, io_mem);

4
hw/fw_cfg.c
View File

@ -266,12 +266,12 @@ void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
register_ioport_write(data_port, 1, 1, fw_cfg_io_writeb, s);
}
if (ctl_addr) {
io_ctl_memory = cpu_register_io_memory(0, fw_cfg_ctl_mem_read,
io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read,
fw_cfg_ctl_mem_write, s);
cpu_register_physical_memory(ctl_addr, FW_CFG_SIZE, io_ctl_memory);
}
if (data_addr) {
io_data_memory = cpu_register_io_memory(0, fw_cfg_data_mem_read,
io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read,
fw_cfg_data_mem_write, s);
cpu_register_physical_memory(data_addr, FW_CFG_SIZE, io_data_memory);
}

2
hw/g364fb.c
View File

@ -608,7 +608,7 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s);
cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
return 0;

4
hw/grackle_pci.c
View File

@ -137,9 +137,9 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
pci_grackle_set_irq, pci_grackle_map_irq,
pic, 0, 4);
pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
pci_grackle_config_write, s);
pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
pci_mem_data = cpu_register_io_memory(pci_grackle_read,
pci_grackle_write, s);
cpu_register_physical_memory(base, 0x1000, pci_mem_config);
cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);

2
hw/gt64xxx.c
View File

@ -1131,7 +1131,7 @@ PCIBus *pci_gt64120_init(qemu_irq *pic)
s->pci->bus = pci_register_bus(NULL, "pci",
pci_gt64120_set_irq, pci_gt64120_map_irq,
pic, 144, 4);
s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);
s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s);
d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
0, gt64120_read_config, gt64120_write_config);

2
hw/heathrow_pic.c
View File

@ -226,7 +226,7 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
s = qemu_mallocz(sizeof(HeathrowPICS));
/* only 1 CPU */
s->irqs = irqs[0];
*pmem_index = cpu_register_io_memory(0, pic_read, pic_write, s);
*pmem_index = cpu_register_io_memory(pic_read, pic_write, s);
register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,
heathrow_pic_load, s);

2
hw/hpet.c
View File

@ -582,7 +582,7 @@ void hpet_init(qemu_irq *irq) {
register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);
qemu_register_reset(hpet_reset, 0, s);
/* HPET Area */
iomemtype = cpu_register_io_memory(0, hpet_ram_read,
iomemtype = cpu_register_io_memory(hpet_ram_read,
hpet_ram_write, s);
cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
}

6
hw/ide.c
View File

@ -3751,7 +3751,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq,
if (dbdma)
DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
pmac_ide_write, d);
register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d);
qemu_register_reset(pmac_ide_reset, 0, d);
@ -3847,8 +3847,8 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
s->dev = ide;
s->shift = shift;
mem1 = cpu_register_io_memory(0, mmio_ide_reads, mmio_ide_writes, s);
mem2 = cpu_register_io_memory(0, mmio_ide_status, mmio_ide_cmd, s);
mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
cpu_register_physical_memory(membase, 16 << shift, mem1);
cpu_register_physical_memory(membase2, 2 << shift, mem2);
}

6
hw/integratorcp.c
View File

@ -256,7 +256,7 @@ static void integratorcm_init(SysBusDevice *dev)
s->cm_init = 0x00000112;
s->flash_offset = qemu_ram_alloc(0x100000);
iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
iomemtype = cpu_register_io_memory(integratorcm_readfn,
integratorcm_writefn, s);
sysbus_init_mmio(dev, 0x00800000, iomemtype);
integratorcm_do_remap(s, 1);
@ -381,7 +381,7 @@ static void icp_pic_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_fiq);
iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
iomemtype = cpu_register_io_memory(icp_pic_readfn,
icp_pic_writefn, s);
sysbus_init_mmio(dev, 0x00800000, iomemtype);
}
@ -433,7 +433,7 @@ static void icp_control_init(uint32_t base)
{
int iomemtype;
iomemtype = cpu_register_io_memory(0, icp_control_readfn,
iomemtype = cpu_register_io_memory(icp_control_readfn,
icp_control_writefn, NULL);
cpu_register_physical_memory(base, 0x00800000, iomemtype);
/* ??? Save/restore. */

2
hw/ioapic.c
View File

@ -250,7 +250,7 @@ IOAPICState *ioapic_init(void)
s = qemu_mallocz(sizeof(IOAPICState));
ioapic_reset(s);
io_memory = cpu_register_io_memory(0, ioapic_mem_read,
io_memory = cpu_register_io_memory(ioapic_mem_read,
ioapic_mem_write, s);
cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);

2
hw/iommu.c
View File

@ -375,7 +375,7 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
s->version = version;
s->irq = irq;
iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
iommu_io_memory = cpu_register_io_memory(iommu_mem_read,
iommu_mem_write, s);
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);

2
hw/isa_mmio.c
View File

@ -96,7 +96,7 @@ static int isa_mmio_iomemtype = 0;
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
{
if (!isa_mmio_iomemtype) {
isa_mmio_iomemtype = cpu_register_io_memory(0, isa_mmio_read,
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
isa_mmio_write, NULL);
}
cpu_register_physical_memory(base, size, isa_mmio_iomemtype);

2
hw/jazz_led.c
View File

@ -307,7 +307,7 @@ void jazz_led_init(target_phys_addr_t base)
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
io = cpu_register_io_memory(0, led_read, led_write, s);
io = cpu_register_io_memory(led_read, led_write, s);
cpu_register_physical_memory(base, 1, io);
s->ds = graphic_console_init(jazz_led_update_display,

4
hw/lsi53c895a.c
View File

@ -1998,9 +1998,9 @@ static void lsi_scsi_init(PCIDevice *dev)
/* Interrupt pin 1 */
pci_conf[0x3d] = 0x01;
s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
s->mmio_io_addr = cpu_register_io_memory(lsi_mmio_readfn,
lsi_mmio_writefn, s);
s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn,
lsi_ram_writefn, s);
pci_register_io_region((struct PCIDevice *)s, 0, 256,

2
hw/m48t59.c
View File

@ -632,7 +632,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
}
if (mem_base != 0) {
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
cpu_register_physical_memory(mem_base, size, s->mem_index);
}
if (type == 59) {

2
hw/mac_dbdma.c
View File

@ -837,7 +837,7 @@ void* DBDMA_init (int *dbdma_mem_index)
s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
*dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, s);
*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);
register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
qemu_register_reset(dbdma_reset, 0, s);
dbdma_reset(s);

2
hw/mac_nvram.c
View File

@ -138,7 +138,7 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
s->size = size;
s->it_shift = it_shift;
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
*mem_index = s->mem_index;
register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,
s);

2
hw/mc146818rtc.c
View File

@ -735,7 +735,7 @@ RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
qemu_mod_timer(s->second_timer2, s->next_second_time);
io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s);
cpu_register_physical_memory(base, 2 << it_shift, io_memory);
register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);

2
hw/mcf5206.c
View File

@ -524,7 +524,7 @@ qemu_irq *mcf5206_init(uint32_t base, CPUState *env)
int iomemtype;
s = (m5206_mbar_state *)qemu_mallocz(sizeof(m5206_mbar_state));
iomemtype = cpu_register_io_memory(0, m5206_mbar_readfn,
iomemtype = cpu_register_io_memory(m5206_mbar_readfn,
m5206_mbar_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);

4
hw/mcf5208.c
View File

@ -176,7 +176,7 @@ static void mcf5208_sys_init(qemu_irq *pic)
QEMUBH *bh;
int i;
iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
iomemtype = cpu_register_io_memory(m5208_sys_readfn,
m5208_sys_writefn, NULL);
/* SDRAMC. */
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
@ -185,7 +185,7 @@ static void mcf5208_sys_init(qemu_irq *pic)
s = (m5208_timer_state *)qemu_mallocz(sizeof(m5208_timer_state));
bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init(bh);
iomemtype = cpu_register_io_memory(0, m5208_timer_readfn,
iomemtype = cpu_register_io_memory(m5208_timer_readfn,
m5208_timer_writefn, s);
cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
iomemtype);

2
hw/mcf_fec.c
View File

@ -458,7 +458,7 @@ void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
s = (mcf_fec_state *)qemu_mallocz(sizeof(mcf_fec_state));
s->irq = irq;
s->mmio_index = cpu_register_io_memory(0, mcf_fec_readfn,
s->mmio_index = cpu_register_io_memory(mcf_fec_readfn,
mcf_fec_writefn, s);
cpu_register_physical_memory(base, 0x400, s->mmio_index);

2
hw/mcf_intc.c
View File

@ -148,7 +148,7 @@ qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
s->env = env;
mcf_intc_reset(s);
iomemtype = cpu_register_io_memory(0, mcf_intc_readfn,
iomemtype = cpu_register_io_memory(mcf_intc_readfn,
mcf_intc_writefn, s);
cpu_register_physical_memory(base, 0x100, iomemtype);

2
hw/mcf_uart.c
View File

@ -303,7 +303,7 @@ void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
int iomemtype;
s = mcf_uart_init(irq, chr);
iomemtype = cpu_register_io_memory(0, mcf_uart_readfn,
iomemtype = cpu_register_io_memory(mcf_uart_readfn,
mcf_uart_writefn, s);
cpu_register_physical_memory(base, 0x40, iomemtype);
}

4
hw/mips_jazz.c
View File

@ -181,7 +181,7 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL);
s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
/* ISA devices */
@ -245,7 +245,7 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Real time clock */
rtc_init(0x70, i8259[8], 1980);
s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
s_rtc = cpu_register_io_memory(rtc_read, rtc_write, env);
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
/* Keyboard (i8042) */

2
hw/mips_malta.c
View File

@ -435,7 +435,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir
s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
malta = cpu_register_io_memory(0, malta_fpga_read,
malta = cpu_register_io_memory(malta_fpga_read,
malta_fpga_write, s);
cpu_register_physical_memory(base, 0x900, malta);

2
hw/mips_r4k.c
View File

@ -185,7 +185,7 @@ void mips_r4k_init (ram_addr_t ram_size,
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
if (!mips_qemu_iomemtype) {
mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
mips_qemu_write, NULL);
}
cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);

2
hw/mpcore.c
View File

@ -268,7 +268,7 @@ static void mpcore_priv_init(SysBusDevice *dev)
int i;
gic_init(&s->gic);
s->iomemtype = cpu_register_io_memory(0, mpcore_priv_readfn,
s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn,
mpcore_priv_writefn, s);
sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
for (i = 0; i < 8; i++) {

2
hw/mst_fpga.c
View File

@ -231,7 +231,7 @@ qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
qi = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
s->pins = qi;
iomemtype = cpu_register_io_memory(0, mst_fpga_readfn,
iomemtype = cpu_register_io_memory(mst_fpga_readfn,
mst_fpga_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
register_savevm("mainstone_fpga", 0, 0, mst_fpga_save, mst_fpga_load, s);

18
hw/musicpal.c
View File

@ -437,7 +437,7 @@ static i2c_interface *musicpal_audio_init(qemu_irq irq)
s->wm = i2c_create_slave(i2c->bus, "wm8750", MP_WM_ADDR);
wm8750_data_req_set(s->wm, audio_callback, s);
iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
iomemtype = cpu_register_io_memory(musicpal_audio_readfn,
musicpal_audio_writefn, s);
cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
@ -756,7 +756,7 @@ static void mv88w8618_eth_init(SysBusDevice *dev)
s->vc = qdev_get_vlan_client(&dev->qdev,
eth_can_receive, eth_receive, NULL,
eth_cleanup, s);
s->mmio_index = cpu_register_io_memory(0, mv88w8618_eth_readfn,
s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
mv88w8618_eth_writefn, s);
sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
}
@ -946,7 +946,7 @@ static void musicpal_lcd_init(SysBusDevice *dev)
musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
musicpal_lcd_writefn, s);
sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype);
@ -1043,7 +1043,7 @@ static void mv88w8618_pic_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
mv88w8618_pic_writefn, s);
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
@ -1167,7 +1167,7 @@ static void mv88w8618_pit_init(SysBusDevice *dev)
mv88w8618_timer_init(dev, &s->timer[i], 1000000);
}
iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
mv88w8618_pit_writefn, s);
sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
}
@ -1224,7 +1224,7 @@ static void mv88w8618_flashcfg_init(SysBusDevice *dev)
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
mv88w8618_flashcfg_writefn, s);
sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
}
@ -1266,7 +1266,7 @@ static void musicpal_misc_init(void)
{
int iomemtype;
iomemtype = cpu_register_io_memory(0, musicpal_misc_readfn,
iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
musicpal_misc_writefn, NULL);
cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
}
@ -1311,7 +1311,7 @@ static void mv88w8618_wlan_init(SysBusDevice *dev)
{
int iomemtype;
iomemtype = cpu_register_io_memory(0, mv88w8618_wlan_readfn,
iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
mv88w8618_wlan_writefn, NULL);
sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
}
@ -1412,7 +1412,7 @@ static void musicpal_gpio_init(void)
{
int iomemtype;
iomemtype = cpu_register_io_memory(0, musicpal_gpio_readfn,
iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
musicpal_gpio_writefn, NULL);
cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype);
}

6
hw/omap.h
View File

@ -1116,7 +1116,7 @@ static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
inline static int debug_register_io_memory(int io_index,
inline static int debug_register_io_memory(
CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
void *opaque)
{
@ -1126,7 +1126,7 @@ inline static int debug_register_io_memory(int io_index,
s->mem_write = mem_write;
s->opaque = opaque;
s->in = 0;
return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
return cpu_register_io_memory(io_readfn, io_writefn, s);
}
# define cpu_register_io_memory debug_register_io_memory
# endif
@ -1136,7 +1136,7 @@ inline static int debug_register_io_memory(int io_index,
# ifdef L4_MUX_HACK
# undef l4_register_io_memory
int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
int l4_register_io_memory(CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write, void *opaque);
# endif

48
hw/omap1.c
View File

@ -425,7 +425,7 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
omap_inth_reset(s);
iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
iomemtype = cpu_register_io_memory(omap_inth_readfn,
omap_inth_writefn, s);
cpu_register_physical_memory(base, size, iomemtype);
@ -645,7 +645,7 @@ struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
omap_inth_reset(s);
iomemtype = cpu_register_io_memory(0, omap2_inth_readfn,
iomemtype = cpu_register_io_memory(omap2_inth_readfn,
omap2_inth_writefn, s);
cpu_register_physical_memory(base, size, iomemtype);
@ -834,7 +834,7 @@ struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
omap_mpu_timer_reset(s);
omap_timer_clk_setup(s);
iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,
omap_mpu_timer_writefn, s);
cpu_register_physical_memory(base, 0x100, iomemtype);
@ -957,7 +957,7 @@ struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
omap_wd_timer_reset(s);
omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,
omap_wd_timer_writefn, s);
cpu_register_physical_memory(base, 0x100, iomemtype);
@ -1059,7 +1059,7 @@ struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
omap_os_timer_reset(s);
omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
iomemtype = cpu_register_io_memory(omap_os_timer_readfn,
omap_os_timer_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -1286,7 +1286,7 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
static void omap_ulpd_pm_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
omap_ulpd_pm_writefn, mpu);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -1501,7 +1501,7 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
static void omap_pin_cfg_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
omap_pin_cfg_writefn, mpu);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -1571,7 +1571,7 @@ static CPUWriteMemoryFunc *omap_id_writefn[] = {
static void omap_id_init(struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
int iomemtype = cpu_register_io_memory(omap_id_readfn,
omap_id_writefn, mpu);
cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
@ -1654,7 +1654,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
static void omap_mpui_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
omap_mpui_writefn, mpu);
cpu_register_physical_memory(base, 0x100, iomemtype);
@ -1763,7 +1763,7 @@ struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
s->abort = abort_irq;
omap_tipb_bridge_reset(s);
iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn,
omap_tipb_bridge_writefn, s);
cpu_register_physical_memory(base, 0x100, iomemtype);
@ -1869,7 +1869,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
static void omap_tcmi_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
omap_tcmi_writefn, mpu);
cpu_register_physical_memory(base, 0x100, iomemtype);
@ -1942,7 +1942,7 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
omap_clk clk)
{
int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
omap_dpll_writefn, s);
s->dpll = clk;
@ -2089,7 +2089,7 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, chr);
int iomemtype = cpu_register_io_memory(0, omap_uart_readfn,
int iomemtype = cpu_register_io_memory(omap_uart_readfn,
omap_uart_writefn, s);
s->ta = ta;
@ -2504,8 +2504,8 @@ static void omap_clkm_init(target_phys_addr_t mpu_base,
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
{
int iomemtype[2] = {
cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s),
cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s),
};
s->clkm.arm_idlect1 = 0x03ff;
@ -2758,7 +2758,7 @@ struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
omap_mpuio_reset(s);
iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
omap_mpuio_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -2954,7 +2954,7 @@ struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
omap_gpio_reset(s);
iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
iomemtype = cpu_register_io_memory(omap_gpio_readfn,
omap_gpio_writefn, s);
cpu_register_physical_memory(base, 0x1000, iomemtype);
@ -3124,7 +3124,7 @@ struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
s->txdrq = dma;
omap_uwire_reset(s);
iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
iomemtype = cpu_register_io_memory(omap_uwire_readfn,
omap_uwire_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -3225,7 +3225,7 @@ static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_pwl_reset(s);
iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
iomemtype = cpu_register_io_memory(omap_pwl_readfn,
omap_pwl_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -3320,7 +3320,7 @@ static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
s->pwt.clk = clk;
omap_pwt_reset(s);
iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
iomemtype = cpu_register_io_memory(omap_pwt_readfn,
omap_pwt_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
}
@ -3743,7 +3743,7 @@ struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
omap_rtc_reset(s);
iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
iomemtype = cpu_register_io_memory(omap_rtc_readfn,
omap_rtc_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -4263,7 +4263,7 @@ struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
omap_mcbsp_reset(s);
iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
omap_mcbsp_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -4435,7 +4435,7 @@ struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
omap_lpg_reset(s);
iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
iomemtype = cpu_register_io_memory(omap_lpg_readfn,
omap_lpg_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -4468,7 +4468,7 @@ static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn,
int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
omap_mpui_io_writefn, mpu);
cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
}

32
hw/omap2.c
View File

@ -483,7 +483,7 @@ struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
omap_gp_timer_reset(s);
omap_gp_timer_clk_setup(s);
iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,
iomemtype = l4_register_io_memory(omap_gp_timer_readfn,
omap_gp_timer_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
@ -554,7 +554,7 @@ void omap_synctimer_init(struct omap_target_agent_s *ta,
struct omap_synctimer_s *s = &mpu->synctimer;
omap_synctimer_reset(s);
omap_l4_attach(ta, 0, l4_register_io_memory(0,
omap_l4_attach(ta, 0, l4_register_io_memory(
omap_synctimer_readfn, omap_synctimer_writefn, s));
}
@ -952,7 +952,7 @@ static void omap_gpio_module_init(struct omap2_gpio_s *s,
s->wkup = wkup;
s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,
iomemtype = l4_register_io_memory(omap_gpio_module_readfn,
omap_gpio_module_writefn, s);
omap_l4_attach(ta, region, iomemtype);
}
@ -1060,7 +1060,7 @@ struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
omap_gpif_reset(s);
iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,
iomemtype = l4_register_io_memory(omap_gpif_top_readfn,
omap_gpif_top_writefn, s);
omap_l4_attach(ta, 1, iomemtype);
@ -1386,7 +1386,7 @@ struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
}
omap_mcspi_reset(s);
iomemtype = l4_register_io_memory(0, omap_mcspi_readfn,
iomemtype = l4_register_io_memory(omap_mcspi_readfn,
omap_mcspi_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
@ -1975,7 +1975,7 @@ struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
#ifdef HAS_AUDIO
AUD_register_card("OMAP EAC", &s->codec.card);
iomemtype = cpu_register_io_memory(0, omap_eac_readfn,
iomemtype = cpu_register_io_memory(omap_eac_readfn,
omap_eac_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
#endif
@ -2160,11 +2160,11 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
s->chr = chr ?: qemu_chr_open("null", "null", NULL);
iomemtype = l4_register_io_memory(0, omap_sti_readfn,
iomemtype = l4_register_io_memory(omap_sti_readfn,
omap_sti_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
omap_sti_fifo_writefn, s);
cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
@ -2204,7 +2204,7 @@ static CPUWriteMemoryFunc **omap_l4_io_writeh_fn;
static CPUWriteMemoryFunc **omap_l4_io_writew_fn;
static void **omap_l4_io_opaque;
int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
int l4_register_io_memory(CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write, void *opaque)
{
omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
@ -2285,7 +2285,7 @@ struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
omap_cpu_io_entry =
cpu_register_io_memory(0, omap_l4_io_readfn,
cpu_register_io_memory(omap_l4_io_readfn,
omap_l4_io_writefn, bus);
# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
@ -2578,7 +2578,7 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
ta->status = 0x00000000;
ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
iomemtype = l4_register_io_memory(0, omap_l4ta_readfn,
iomemtype = l4_register_io_memory(omap_l4ta_readfn,
omap_l4ta_writefn, ta);
ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
@ -2708,7 +2708,7 @@ static CPUWriteMemoryFunc *omap_tap_writefn[] = {
void omap_tap_init(struct omap_target_agent_s *ta,
struct omap_mpu_state_s *mpu)
{
omap_l4_attach(ta, 0, l4_register_io_memory(0,
omap_l4_attach(ta, 0, l4_register_io_memory(
omap_tap_readfn, omap_tap_writefn, mpu));
}
@ -3521,7 +3521,7 @@ struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
s->mpu = mpu;
omap_prcm_coldreset(s);
iomemtype = l4_register_io_memory(0, omap_prcm_readfn,
iomemtype = l4_register_io_memory(omap_prcm_readfn,
omap_prcm_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
omap_l4_attach(ta, 1, iomemtype);
@ -3891,7 +3891,7 @@ struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
s->mpu = mpu;
omap_sysctl_reset(s);
iomemtype = l4_register_io_memory(0, omap_sysctl_readfn,
iomemtype = l4_register_io_memory(omap_sysctl_readfn,
omap_sysctl_writefn, s);
omap_l4_attach(ta, 0, iomemtype);
@ -4035,7 +4035,7 @@ struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
omap_sdrc_reset(s);
iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn,
iomemtype = cpu_register_io_memory(omap_sdrc_readfn,
omap_sdrc_writefn, s);
cpu_register_physical_memory(base, 0x1000, iomemtype);
@ -4409,7 +4409,7 @@ struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
omap_gpmc_reset(s);
iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn,
iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
omap_gpmc_writefn, s);
cpu_register_physical_memory(base, 0x1000, iomemtype);

4
hw/omap_dma.c
View File

@ -1655,7 +1655,7 @@ struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, 1);
iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
iomemtype = cpu_register_io_memory(omap_dma_readfn,
omap_dma_writefn, s);
cpu_register_physical_memory(base, memsize, iomemtype);
@ -2062,7 +2062,7 @@ struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, !!s->dma->freq);
iomemtype = cpu_register_io_memory(0, omap_dma4_readfn,
iomemtype = cpu_register_io_memory(omap_dma4_readfn,
omap_dma4_writefn, s);
cpu_register_physical_memory(base, 0x1000, iomemtype);

10
hw/omap_dss.c
View File

@ -1037,15 +1037,15 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
s->drq = drq;
omap_dss_reset(s);
iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn,
iomemtype[0] = l4_register_io_memory(omap_diss1_readfn,
omap_diss1_writefn, s);
iomemtype[1] = l4_register_io_memory(0, omap_disc1_readfn,
iomemtype[1] = l4_register_io_memory(omap_disc1_readfn,
omap_disc1_writefn, s);
iomemtype[2] = l4_register_io_memory(0, omap_rfbi1_readfn,
iomemtype[2] = l4_register_io_memory(omap_rfbi1_readfn,
omap_rfbi1_writefn, s);
iomemtype[3] = l4_register_io_memory(0, omap_venc1_readfn,
iomemtype[3] = l4_register_io_memory(omap_venc1_readfn,
omap_venc1_writefn, s);
iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn,
iomemtype[4] = cpu_register_io_memory(omap_im3_readfn,
omap_im3_writefn, s);
omap_l4_attach(ta, 0, iomemtype[0]);
omap_l4_attach(ta, 1, iomemtype[1]);

4
hw/omap_i2c.c
View File

@ -436,7 +436,7 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
iomemtype = cpu_register_io_memory(omap_i2c_readfn,
omap_i2c_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -457,7 +457,7 @@ struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
iomemtype = l4_register_io_memory(0, omap_i2c_readfn,
iomemtype = l4_register_io_memory(omap_i2c_readfn,
omap_i2c_writefn, s);
omap_l4_attach(ta, 0, iomemtype);

2
hw/omap_lcdc.c
View File

@ -450,7 +450,7 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
s->emiff_base = emiff_base;
omap_lcdc_reset(s);
iomemtype = cpu_register_io_memory(0, omap_lcdc_readfn,
iomemtype = cpu_register_io_memory(omap_lcdc_readfn,
omap_lcdc_writefn, s);
cpu_register_physical_memory(base, 0x100, iomemtype);

4
hw/omap_mmc.c
View File

@ -586,7 +586,7 @@ struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
omap_mmc_reset(s);
iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
iomemtype = cpu_register_io_memory(omap_mmc_readfn,
omap_mmc_writefn, s);
cpu_register_physical_memory(base, 0x800, iomemtype);
@ -612,7 +612,7 @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
omap_mmc_reset(s);
iomemtype = l4_register_io_memory(0, omap_mmc_readfn,
iomemtype = l4_register_io_memory(omap_mmc_readfn,
omap_mmc_writefn, s);
omap_l4_attach(ta, 0, iomemtype);

10
hw/omap_sx1.c
View File

@ -142,12 +142,12 @@ static void sx1_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
(phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs0val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val);
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
OMAP_CS0_SIZE - flash_size, io);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs2val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val);
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs3val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val);
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
fl_idx = 0;
@ -167,7 +167,7 @@ static void sx1_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,
(phys_flash = qemu_ram_alloc(flash1_size)) |
IO_MEM_ROM);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
OMAP_CS1_SIZE - flash1_size, io);
@ -179,7 +179,7 @@ static void sx1_init(ram_addr_t ram_size,
}
fl_idx++;
} else {
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
}

2
hw/onenand.c
View File

@ -631,7 +631,7 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq)
s->secs = size >> 9;
s->blockwp = qemu_malloc(s->blocks);
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0;
s->iomemtype = cpu_register_io_memory(0, onenand_readfn,
s->iomemtype = cpu_register_io_memory(onenand_readfn,
onenand_writefn, s);
if (bdrv_index == -1)
s->image = memset(qemu_malloc(size + (size >> 5)),

6
hw/openpic.c
View File

@ -1046,7 +1046,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
#if 0 // Don't implement ISU for now
opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
opp_io_memory = cpu_register_io_memory(openpic_src_read,
openpic_src_write);
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
opp_io_memory);
@ -1217,7 +1217,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
} else {
opp = qemu_mallocz(sizeof(openpic_t));
}
opp->mem_index = cpu_register_io_memory(0, openpic_read,
opp->mem_index = cpu_register_io_memory(openpic_read,
openpic_write, opp);
// isu_base &= 0xFFFC0000;
@ -1687,7 +1687,7 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
int mem_index;
mem_index = cpu_register_io_memory(0, list[i].read, list[i].write, mpp);
mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp);
if (mem_index < 0) {
goto free;
}

8
hw/palm.c
View File

@ -216,14 +216,14 @@ static void palmte_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
(phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs0val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val);
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
OMAP_CS0_SIZE - flash_size, io);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs2val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val);
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs3val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val);
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
palmte_microwire_setup(cpu);

2
hw/parallel.c
View File

@ -543,7 +543,7 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
parallel_reset(s);
qemu_register_reset(parallel_reset, 0, s);
io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
return s;
}

2
hw/pckbd.c
View File

@ -430,7 +430,7 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
kbd_reset(s);
register_savevm("pckbd", 0, 3, kbd_save, kbd_load, s);
s_io_memory = cpu_register_io_memory(0, kbd_mm_read, kbd_mm_write, s);
s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
cpu_register_physical_memory(base, size, s_io_memory);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);

4
hw/pcnet.c
View File

@ -2048,7 +2048,7 @@ static void pci_pcnet_init(PCIDevice *pci_dev)
/* Handler for memory-mapped I/O */
s->mmio_index =
cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, &d->state);
cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state);
pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);
@ -2126,7 +2126,7 @@ static void lance_init(SysBusDevice *dev)
PCNetState *s = &d->state;
s->mmio_index =
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
cpu_register_io_memory(lance_mem_read, lance_mem_write, d);
s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma");

2
hw/pflash_cfi01.c
View File

@ -522,7 +522,7 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
/* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off);
pfl->fl_mem = cpu_register_io_memory(0,
pfl->fl_mem = cpu_register_io_memory(
pflash_read_ops, pflash_write_ops, pfl);
pfl->off = off;
cpu_register_physical_memory(base, total_len,

2
hw/pflash_cfi02.c
View File

@ -559,7 +559,7 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
pfl = qemu_mallocz(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off);
pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops, pflash_write_ops,
pfl);
pfl->off = off;
pfl->base = base;

2
hw/pl011.c
View File

@ -291,7 +291,7 @@ static void pl011_init(SysBusDevice *dev, const unsigned char *id)
int iomemtype;
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
iomemtype = cpu_register_io_memory(0, pl011_readfn,
iomemtype = cpu_register_io_memory(pl011_readfn,
pl011_writefn, s);
sysbus_init_mmio(dev, 0x1000,iomemtype);
sysbus_init_irq(dev, &s->irq);

2
hw/pl022.c
View File

@ -293,7 +293,7 @@ static void pl022_init(SysBusDevice *dev)
pl022_state *s = FROM_SYSBUS(pl022_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(0, pl022_readfn,
iomemtype = cpu_register_io_memory(pl022_readfn,
pl022_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);

2
hw/pl031.c
View File

@ -189,7 +189,7 @@ static void pl031_init(SysBusDevice *dev)
pl031_state *s = FROM_SYSBUS(pl031_state, dev);
struct tm tm;
iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s);
if (iomemtype == -1) {
hw_error("pl031_init: Can't register I/O memory\n");
}

2
hw/pl050.c
View File

@ -127,7 +127,7 @@ static void pl050_init(SysBusDevice *dev, int is_mouse)
pl050_state *s = FROM_SYSBUS(pl050_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(0, pl050_readfn,
iomemtype = cpu_register_io_memory(pl050_readfn,
pl050_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);

2
hw/pl061.c
View File

@ -296,7 +296,7 @@ static void pl061_init(SysBusDevice *dev)
int iomemtype;
pl061_state *s = FROM_SYSBUS(pl061_state, dev);
iomemtype = cpu_register_io_memory(0, pl061_readfn,
iomemtype = cpu_register_io_memory(pl061_readfn,
pl061_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);

2
hw/pl080.c
View File

@ -324,7 +324,7 @@ static void pl08x_init(SysBusDevice *dev, int nchannels)
int iomemtype;
pl080_state *s = FROM_SYSBUS(pl080_state, dev);
iomemtype = cpu_register_io_memory(0, pl080_readfn,
iomemtype = cpu_register_io_memory(pl080_readfn,
pl080_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);

2
hw/pl110.c
View File

@ -354,7 +354,7 @@ static void pl110_init(SysBusDevice *dev)
pl110_state *s = FROM_SYSBUS(pl110_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(0, pl110_readfn,
iomemtype = cpu_register_io_memory(pl110_readfn,
pl110_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);

2
hw/pl181.c
View File

@ -451,7 +451,7 @@ static void pl181_init(SysBusDevice *dev)
pl181_state *s = FROM_SYSBUS(pl181_state, dev);
BlockDriverState *bd;
iomemtype = cpu_register_io_memory(0, pl181_readfn,
iomemtype = cpu_register_io_memory(pl181_readfn,
pl181_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq[0]);

2
hw/pl190.c
View File

@ -232,7 +232,7 @@ static void pl190_init(SysBusDevice *dev)
pl190_state *s = FROM_SYSBUS(pl190_state, dev);
int iomemtype;
iomemtype = cpu_register_io_memory(0, pl190_readfn,
iomemtype = cpu_register_io_memory(pl190_readfn,
pl190_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);

4
hw/ppc405_boards.c
View File

@ -161,7 +161,7 @@ static void ref405ep_fpga_init (uint32_t base)
int fpga_memory;
fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
ref405ep_fpga_write, fpga);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
ref405ep_fpga_reset(fpga);
@ -485,7 +485,7 @@ static void taihu_cpld_init (uint32_t base)
int cpld_memory;
cpld = qemu_mallocz(sizeof(taihu_cpld_t));
cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
cpld_memory = cpu_register_io_memory(taihu_cpld_read,
taihu_cpld_write, cpld);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
taihu_cpld_reset(cpld);

2
hw/ppc4xx_devs.c
View File

@ -247,7 +247,7 @@ ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
mmio->base = base;
mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
mmio_memory = cpu_register_io_memory(mmio_read, mmio_write, mmio);
#if defined(DEBUG_MMIO)
printf("%s: base " PADDRX " len %08x %d\n", __func__,
base, TARGET_PAGE_SIZE, mmio_memory);

6
hw/ppc4xx_pci.c
View File

@ -384,14 +384,14 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
/* CFGADDR */
index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,
index = cpu_register_io_memory(pci4xx_cfgaddr_read,
pci4xx_cfgaddr_write, controller);
if (index < 0)
goto free;
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
/* CFGDATA */
index = cpu_register_io_memory(0, pci4xx_cfgdata_read,
index = cpu_register_io_memory(pci4xx_cfgdata_read,
pci4xx_cfgdata_write,
&controller->pci_state);
if (index < 0)
@ -399,7 +399,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
/* Internal registers */
index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, controller);
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller);
if (index < 0)
goto free;
cpu_register_physical_memory(registers, PCI_REG_SIZE, index);

2
hw/ppc_newworld.c
View File

@ -246,7 +246,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
isa_mmio_init(0xf2000000, 0x00800000);
/* UniN init */
unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL);
cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));

6
hw/ppc_prep.c
View File

@ -659,7 +659,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
pci_bus = pci_prep_init(i8259);
// pci_bus = i440fx_init();
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
PPC_prep_io_write, sysctrl);
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
@ -728,12 +728,12 @@ static void ppc_prep_init (ram_addr_t ram_size,
register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
/* PCI intack location */
PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
PPC_intack_write, NULL);
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
/* PowerPC control and status register group */
#if 0
PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
NULL);
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
#endif

6
hw/ppce500_pci.c
View File

@ -332,21 +332,21 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
controller->pci_dev = d;
/* CFGADDR */
index = cpu_register_io_memory(0, pcie500_cfgaddr_read,
index = cpu_register_io_memory(pcie500_cfgaddr_read,
pcie500_cfgaddr_write, controller);
if (index < 0)
goto free;
cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
/* CFGDATA */
index = cpu_register_io_memory(0, pcie500_cfgdata_read,
index = cpu_register_io_memory(pcie500_cfgdata_read,
pcie500_cfgdata_write,
&controller->pci_state);
if (index < 0)
goto free;
cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
index = cpu_register_io_memory(0, e500_pci_reg_read,
index = cpu_register_io_memory(e500_pci_reg_read,
e500_pci_reg_write, controller);
if (index < 0)
goto free;

2
hw/prep_pci.c
View File

@ -149,7 +149,7 @@ PCIBus *pci_prep_init(qemu_irq *pic)
register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
PPC_PCIIO_write, s);
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);

24
hw/pxa2xx.c
View File

@ -857,7 +857,7 @@ static void pxa2xx_ssp_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype);
register_savevm("pxa2xx_ssp", -1, 0,
@ -1509,7 +1509,7 @@ PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
s->bus = i2c_init_bus(NULL, "i2c");
s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
pxa2xx_i2c_writefn, s);
cpu_register_physical_memory(base & ~region_size,
region_size + 1, iomemtype);
@ -1747,7 +1747,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
pxa2xx_i2s_reset(s);
iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
pxa2xx_i2s_writefn, s);
cpu_register_physical_memory(base, 0x100000, iomemtype);
@ -2006,7 +2006,7 @@ static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
pxa2xx_fir_reset(s);
iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
pxa2xx_fir_writefn, s);
cpu_register_physical_memory(base, 0x1000, iomemtype);
@ -2090,7 +2090,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
@ -2101,13 +2101,13 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
s->mm_regs[MDMRS >> 2] = 0x00020002;
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
pxa2xx_mm_writefn, s);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
pxa2xx_pm_writefn, s);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
@ -2129,7 +2129,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
pxa2xx_rtc_writefn, s);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
@ -2202,7 +2202,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
register_savevm("pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
@ -2213,13 +2213,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
s->mm_regs[MDMRS >> 2] = 0x00020002;
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
pxa2xx_mm_writefn, s);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
register_savevm("pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
pxa2xx_pm_writefn, s);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
@ -2241,7 +2241,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
pxa2xx_rtc_writefn, s);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);

2
hw/pxa2xx_dma.c
View File

@ -503,7 +503,7 @@ static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
iomemtype = cpu_register_io_memory(0, pxa2xx_dma_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn,
pxa2xx_dma_writefn, s);
cpu_register_physical_memory(base, 0x00010000, iomemtype);

2
hw/pxa2xx_gpio.c
View File

@ -308,7 +308,7 @@ PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
s->cpu_env = env;
s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines);
iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn,
pxa2xx_gpio_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);

2
hw/pxa2xx_keypad.c
View File

@ -313,7 +313,7 @@ PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
s = (PXA2xxKeyPadState *) qemu_mallocz(sizeof(PXA2xxKeyPadState));
s->irq = irq;
iomemtype = cpu_register_io_memory(0, pxa2xx_keypad_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_keypad_readfn,
pxa2xx_keypad_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);

2
hw/pxa2xx_lcd.c
View File

@ -928,7 +928,7 @@ PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
pxa2xx_lcdc_orientation(s, graphic_rotate);
iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn,
pxa2xx_lcdc_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);

2
hw/pxa2xx_mmci.c
View File

@ -527,7 +527,7 @@ PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
s->irq = irq;
s->dma = dma;
iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_mmci_readfn,
pxa2xx_mmci_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);

6
hw/pxa2xx_pcmcia.c
View File

@ -139,19 +139,19 @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base)
qemu_mallocz(sizeof(PXA2xxPCMCIAState));
/* Socket I/O Memory Space */
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_io_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_io_readfn,
pxa2xx_pcmcia_io_writefn, s);
cpu_register_physical_memory(base | 0x00000000, 0x04000000, iomemtype);
/* Then next 64 MB is reserved */
/* Socket Attribute Memory Space */
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_attr_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_attr_readfn,
pxa2xx_pcmcia_attr_writefn, s);
cpu_register_physical_memory(base | 0x08000000, 0x04000000, iomemtype);
/* Socket Common Memory Space */
iomemtype = cpu_register_io_memory(0, pxa2xx_pcmcia_common_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_pcmcia_common_readfn,
pxa2xx_pcmcia_common_writefn, s);
cpu_register_physical_memory(base | 0x0c000000, 0x04000000, iomemtype);

2
hw/pxa2xx_pic.c
View File

@ -299,7 +299,7 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
qi = qemu_allocate_irqs(pxa2xx_pic_set_irq, s, PXA2XX_PIC_SRCS);
/* Enable IC memory-mapped registers access. */
iomemtype = cpu_register_io_memory(0, pxa2xx_pic_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn,
pxa2xx_pic_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);

2
hw/pxa2xx_timer.c
View File

@ -451,7 +451,7 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
pxa2xx_timer_tick, &s->timer[i]);
}
iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
pxa2xx_timer_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);

2
hw/r2d.c
View File

@ -176,7 +176,7 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
s->irl = irl;
iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
r2d_fpga_writefn, s);
cpu_register_physical_memory(base, 0x40, iomemtype);
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);

4
hw/rc4030.c
View File

@ -814,9 +814,9 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);
rc4030_reset(s);
s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s);
s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);
cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s);
s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s);
cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
return s;

2
hw/realview_gic.c
View File

@ -63,7 +63,7 @@ static void realview_gic_init(SysBusDevice *dev)
RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
gic_init(&s->gic);
s->iomemtype = cpu_register_io_memory(0, realview_gic_cpu_readfn,
s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn,
realview_gic_cpu_writefn, s);
sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
}

2
hw/rtl8139.c
View File

@ -3469,7 +3469,7 @@ static void pci_rtl8139_init(PCIDevice *dev)
/* I/O handler for memory-mapped I/O */
s->rtl8139_mmio_io_addr =
cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s);
pci_register_io_region(&d->dev, 0, 0x100,
PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);

2
hw/sbi.c
View File

@ -151,7 +151,7 @@ void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
s->cpu_irqs[i] = parent_irq[i];
}
sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s);
sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s);
cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);

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