Handle suspend in qemu (Gleb Natapov)
Reset a PC and tell BIOS that resume from ram is required on the next boot. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6080 c046a42c-6fe2-441c-8c8c-71466251a162
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23
hw/acpi.c
23
hw/acpi.c
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@ -53,6 +53,8 @@ typedef struct PIIX4PMState {
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qemu_irq irq;
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qemu_irq irq;
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} PIIX4PMState;
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} PIIX4PMState;
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#define RSM_STS (1 << 15)
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#define PWRBTN_STS (1 << 8)
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#define RTC_EN (1 << 10)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define GBL_EN (1 << 5)
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@ -151,6 +153,14 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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case 0: /* soft power off */
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case 0: /* soft power off */
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qemu_system_shutdown_request();
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qemu_system_shutdown_request();
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break;
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break;
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case 1:
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/* RSM_STS should be set on resume. Pretend that resume
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was caused by power button */
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s->pmsts |= (RSM_STS | PWRBTN_STS);
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qemu_system_reset_request();
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#if defined(TARGET_I386)
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cmos_set_s3_resume();
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#endif
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default:
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default:
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break;
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break;
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}
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}
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@ -471,6 +481,17 @@ static int pm_load(QEMUFile* f,void* opaque,int version_id)
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return 0;
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return 0;
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}
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}
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static void piix4_reset(void *opaque)
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{
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PIIX4PMState *s = opaque;
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uint8_t *pci_conf = s->dev.config;
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pci_conf[0x58] = 0;
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pci_conf[0x59] = 0;
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pci_conf[0x5a] = 0;
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pci_conf[0x5b] = 0;
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}
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq)
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qemu_irq sci_irq)
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{
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{
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@ -527,6 +548,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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s->smbus = i2c_init_bus();
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s->smbus = i2c_init_bus();
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s->irq = sci_irq;
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s->irq = sci_irq;
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qemu_register_reset(piix4_reset, s);
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return s->smbus;
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return s->smbus;
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}
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}
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8
hw/pc.c
8
hw/pc.c
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@ -1135,6 +1135,14 @@ static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
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initrd_filename, 0, cpu_model);
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initrd_filename, 0, cpu_model);
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}
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}
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/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
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BIOS will read it and start S3 resume at POST Entry */
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void cmos_set_s3_resume(void)
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{
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if (rtc_state)
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rtc_set_memory(rtc_state, 0xF, 0xFE);
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}
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QEMUMachine pc_machine = {
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QEMUMachine pc_machine = {
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.name = "pc",
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.name = "pc",
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.desc = "Standard PC",
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.desc = "Standard PC",
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1
hw/pc.h
1
hw/pc.h
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@ -82,6 +82,7 @@ RTCState *rtc_init(int base, qemu_irq irq);
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RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
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RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
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void rtc_set_memory(RTCState *s, int addr, int val);
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void rtc_set_memory(RTCState *s, int addr, int val);
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void rtc_set_date(RTCState *s, const struct tm *tm);
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void rtc_set_date(RTCState *s, const struct tm *tm);
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void cmos_set_s3_resume(void);
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/* pc.c */
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/* pc.c */
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extern int fd_bootchk;
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extern int fd_bootchk;
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