cc32rs512: add simulation of the built-in flash controller
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a4fb8f496a
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0aafdf2366
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hw/cc32rs512.c
220
hw/cc32rs512.c
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@ -23,6 +23,201 @@
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#include "boards.h"
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#include "exec-memory.h"
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/***********************************************************************
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* Flash controller
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***********************************************************************/
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enum cc32_flcon_reg {
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FLCON = 0x00,
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FLSDP1 = 0x04,
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FLSDP2 = 0x08,
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FLSTS = 0x0C,
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FLBUF = 0x10,
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};
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#define NUM_FL_REGS ((FLBUF>>2) + 4)
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enum write_state {
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WRST_NONE,
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WRST_SDP1_55,
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WRST_SDP1_AA,
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WRST_ERASE,
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WRST_PROGRAM,
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};
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typedef struct cc32_flcon_state {
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SysBusDevice busdev;
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t regs[NUM_FL_REGS];
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enum write_state wrst;
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uint8_t *storage;
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uint8_t *ram_storage;
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} cc32_flcon_state;
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static void cc32_flcon_update(cc32_flcon_state *s)
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{
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if (s->regs[FLSTS>>2] & 1)
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qemu_set_irq(s->irq, 1);
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else
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qemu_set_irq(s->irq, 0);
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}
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static uint64_t cc32_flcon_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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cc32_flcon_state *s = (cc32_flcon_state *)opaque;
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return s->regs[offset>>2];
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}
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static void cc32_flcon_write(void *opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size)
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{
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cc32_flcon_state *s = (cc32_flcon_state *)opaque;
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s->regs[offset>>2] = value;
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switch (offset) {
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case FLSDP1:
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switch (value) {
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case 0x55:
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s->wrst = WRST_SDP1_55;
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break;
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case 0xAA:
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s->wrst = WRST_SDP1_AA;
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break;
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default:
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/* Signal incorrect operation */
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s->regs[FLSTS>>2] |= (1 << 1);
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s->wrst = WRST_NONE;
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break;
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}
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break;
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case FLSDP2:
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if (s->wrst == WRST_SDP1_55 && (value == 0xAA)) {
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s->wrst = WRST_ERASE;
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/* actual ERASE will be performed once the program
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* writes a 0xFF to any address within the flash page */
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} else if ((s->wrst == WRST_SDP1_AA) && (value == 0x55)) {
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s->wrst = WRST_PROGRAM;
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/* actual PROGRAM will be performed once the program
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* writes a 0x00 to any address within the flash page */
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} else {
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/* Signal incorrect operation */
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s->regs[FLSTS>>2] |= (1 << 1);
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s->wrst = WRST_NONE;
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break;
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}
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break;
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case FLSTS:
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/* clear bits */
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s->regs[offset>>2] &= ~(value & 3);
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break;
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}
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cc32_flcon_update(s);
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}
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/* callback for user writes to the flash memory region */
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static void cc32_flash_write(void *opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size)
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{
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cc32_flcon_state *s = (cc32_flcon_state *)opaque;
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uint32_t epsize = (s->regs[FLCON>>2] >> 3);
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uint32_t page_size, mask;
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if (epsize == 0) {
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page_size = 512;
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mask = 0xfffffe00;
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} else {
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page_size = 256;
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mask = 0xffffff00;
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}
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/* FIXME: check for 0x00 / 0xFF as value */
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switch (s->wrst) {
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case WRST_ERASE:
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fprintf(stderr, "cc32-flcon: Erasing %u at offset 0x%06x\n",
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page_size, offset & mask);
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memset(s->storage + (offset & mask), 0xFF, page_size);
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s->regs[FLSTS>>2] |= 1;
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s->wrst = WRST_NONE;
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break;
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case WRST_PROGRAM:
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fprintf(stderr, "cc32-flcon: Programming %u at offset 0x%06x\n",
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page_size, offset & mask);
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memcpy(s->storage + (offset & mask),
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s->ram_storage + ((s->regs[FLBUF>>2] & 0xffffff) - 0xC0000),
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page_size);
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s->regs[FLSTS>>2] |= 1;
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s->wrst = WRST_NONE;
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break;
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default:
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break;
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}
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cc32_flcon_update(s);
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}
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/* MMIO interface of the FLCON */
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static const MemoryRegionOps cc32_flcon_ops = {
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.read = cc32_flcon_read,
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.write = cc32_flcon_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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/* Flash memory writes for memory_region_init_rom_device() */
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static const MemoryRegionOps cc32_flash_ops = {
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.write = cc32_flash_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int cc32_flcon_init(SysBusDevice *dev)
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{
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cc32_flcon_state *s = FROM_SYSBUS(cc32_flcon_state, dev);
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sysbus_init_irq(dev, &s->irq);
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memory_region_init_io(&s->iomem, &cc32_flcon_ops, s, "cc32-flcon", NUM_FL_REGS<<2);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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static void cc32_flcon_reset(DeviceState *d)
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{
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cc32_flcon_state *s = container_of(d, cc32_flcon_state, busdev.qdev);
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s->regs[FLBUF>>2] = 0xC0000 + (16*1024) - 512;
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}
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static void cc32_flcon_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
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sdc->init = cc32_flcon_init;
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dc->reset = cc32_flcon_reset;
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}
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static TypeInfo cc32_flcon_info = {
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.name = "cc32-flcon",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(cc32_flcon_state),
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.class_init = cc32_flcon_class_init,
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};
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/***********************************************************************
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* System controller
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***********************************************************************/
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enum cc32_sysc_reg {
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SCCM0 = 0x00,
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SCSYS = 0x04,
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@ -42,7 +237,7 @@ enum cc32_sysc_reg {
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SCCM4 = 0x7C,
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};
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#define NUM_REGS (SCCM4 + 4)
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#define NUM_REGS ((SCCM4>>2) + 4)
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typedef struct cc32_sysc_state
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{
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@ -105,6 +300,7 @@ static void cc32_sysc_write(void *opaque, target_phys_addr_t offset,
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switch (offset) {
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case SCINTEN:
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s->irq_enabled = value;
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fprintf(stderr, "cc32-sysc: INTEN = 0x%08x\n", s->irq_enabled);
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break;
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}
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cc32_sysc_update(s);
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@ -123,7 +319,7 @@ static int cc32_sysc_init(SysBusDevice *dev)
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qdev_init_gpio_in(&dev->qdev, cc32_sysc_set_irq, 32);
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sysbus_init_irq(dev, &s->parent_irq);
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sysbus_init_irq(dev, &s->parent_fiq);
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memory_region_init_io(&s->iomem, &cc32_sysc_ops, s, "cc32-sysc", 8);
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memory_region_init_io(&s->iomem, &cc32_sysc_ops, s, "cc32-sysc", NUM_REGS<<2);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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@ -156,11 +352,16 @@ static TypeInfo cc32_sysc_info = {
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static void cc32_register_types(void)
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{
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type_register_static(&cc32_sysc_info);
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type_register_static(&cc32_flcon_info);
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}
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type_init(cc32_register_types)
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/***********************************************************************
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* SoC core
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***********************************************************************/
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struct arm_boot_info cc32rs512_binfo;
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@ -177,6 +378,7 @@ static void cc32rs512_init(ram_addr_t ram_size,
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qemu_irq *cpu_irq;
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qemu_irq pic[32];
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DeviceState *dev;
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cc32_flcon_state *fl;
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int i;
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if (!cpu_model)
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@ -187,13 +389,12 @@ static void cc32rs512_init(ram_addr_t ram_size,
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exit(1);
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}
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memory_region_init_ram(flash, "cc32rs512.flash", 512*1024);
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memory_region_add_subregion(sysmem, 0, flash);
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memory_region_init_ram(ram, "cc32rs512.ram", 16*1024);
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vmstate_register_ram_global(ram);
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memory_region_add_subregion(sysmem, 0xc0000, ram);
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memory_region_init_ram(rsa_ram, "cc32rs512.rsa_ram", 2*1024);
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vmstate_register_ram_global(rsa_ram);
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memory_region_add_subregion(sysmem, 0xd4000, rsa_ram);
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cc32rs512_binfo.ram_size = ram_size;
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@ -209,6 +410,15 @@ static void cc32rs512_init(ram_addr_t ram_size,
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sysbus_create_simple("cc32-iso-slave", 0x0F8800, pic[8]);
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dev = sysbus_create_simple("cc32-flcon", 0x0F2000, pic[6]);
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fl = container_of(dev, cc32_flcon_state, busdev.qdev);
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memory_region_init_rom_device(flash, &cc32_flash_ops, fl,
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"cc32rs512.flash", 512*1024);
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vmstate_register_ram_global(flash);
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fl->storage = memory_region_get_ram_ptr(flash);
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fl->ram_storage = memory_region_get_ram_ptr(ram);
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memory_region_add_subregion(sysmem, 0, flash);
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arm_load_kernel(env, &cc32rs512_binfo);
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}
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