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osmo-ccid-firmware
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add 20 MHz clock output 

use GCLK5 to output 20 MHz clock on PA11/GCLK_IO[5] for SIM cards
clock.
this can be further divided by the NCN8025 before reaching the SIM.

Change-Id: I2c0d6a31ec63a87e04ef4e3afbedce3a221324cc
This commit is contained in:
Kevin Redon 2019-01-30 18:54:59 +01:00
parent 4e39b0194f
commit d4ed1ec9ff
2 changed files with 10 additions and 10 deletions
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10
sysmoOCTSIM/atmel_start_config.atstart
View File

@ -648,7 +648,7 @@ drivers:
enable_gclk_gen_2: true
enable_gclk_gen_3: true
enable_gclk_gen_4: false
enable_gclk_gen_5: false
enable_gclk_gen_5: true
enable_gclk_gen_6: false
enable_gclk_gen_7: false
enable_gclk_gen_8: false
@ -688,9 +688,9 @@ drivers:
gclk_arch_gen_4_oe: false
gclk_arch_gen_4_oov: false
gclk_arch_gen_4_runstdby: false
gclk_arch_gen_5_enable: false
gclk_arch_gen_5_enable: true
gclk_arch_gen_5_idc: false
gclk_arch_gen_5_oe: false
gclk_arch_gen_5_oe: true
gclk_arch_gen_5_oov: false
gclk_arch_gen_5_runstdby: false
gclk_arch_gen_6_enable: false
@ -734,9 +734,9 @@ drivers:
gclk_gen_4_div: 1
gclk_gen_4_div_sel: false
gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
gclk_gen_5_div: 1
gclk_gen_5_div: 5
gclk_gen_5_div_sel: false
gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
gclk_gen_5_oscillator: Digital Phase Locked Loop (DPLL1)
gclk_gen_6_div: 1
gclk_gen_6_div_sel: false
gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)

10
sysmoOCTSIM/config/hpl_gclk_config.h
View File

@ -387,7 +387,7 @@
// <i> Indicates whether generic clock 5 configuration is enabled or not
// <id> enable_gclk_gen_5
#ifndef CONF_GCLK_GENERATOR_5_CONFIG
#define CONF_GCLK_GENERATOR_5_CONFIG 0
#define CONF_GCLK_GENERATOR_5_CONFIG 1
#endif
// <h> Generic Clock Generator Control
@ -404,7 +404,7 @@
// <i> This defines the clock source for generic clock generator 5
// <id> gclk_gen_5_oscillator
#ifndef CONF_GCLK_GEN_5_SOURCE
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1
#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DPLL1
#endif
// <q> Run in Standby
@ -425,7 +425,7 @@
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_5_oe
#ifndef CONF_GCLK_GEN_5_OE
#define CONF_GCLK_GEN_5_OE 0
#define CONF_GCLK_GEN_5_OE 1
#endif
// <q> Output Off Value
@ -446,7 +446,7 @@
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_5_enable
#ifndef CONF_GCLK_GEN_5_GENEN
#define CONF_GCLK_GEN_5_GENEN 0
#define CONF_GCLK_GEN_5_GENEN 1
#endif
// </h>
@ -454,7 +454,7 @@
//<o> Generic clock generator 5 division <0x0000-0xFFFF>
// <id> gclk_gen_5_div
#ifndef CONF_GCLK_GEN_5_DIV
#define CONF_GCLK_GEN_5_DIV 1
#define CONF_GCLK_GEN_5_DIV 5
#endif
// </h>
// </e>