fix icc clock setting

Change-Id: Ife540c1efa6accd95d85e66e3ae346824450f4fe
This commit is contained in:
Eric Wild 2019-10-31 17:47:47 +01:00
parent a347274dd1
commit b4c4e5c876
3 changed files with 10 additions and 6 deletions

View File

@ -120,7 +120,7 @@ static void iso_fsm_clot_user_cb(struct osmo_fsm_inst *fi, int event, int cause,
uint8_t D = iso7816_3_di_table[cs->proposed_pars.di];
uint32_t fmax = iso7816_3_fmax_table[cs->proposed_pars.fi];
card_uart_ctrl(ss->cuart, CUART_CTL_CLOCK, fmax);
card_uart_ctrl(ss->cuart, CUART_CTL_CLOCK_FREQ, fmax);
card_uart_ctrl(ss->cuart, CUART_CTL_FD, F/D);
card_uart_ctrl(ss->cuart, CUART_CTL_WTIME, cs->proposed_pars.t0.waiting_integer);

View File

@ -25,6 +25,7 @@ enum card_uart_ctl {
CUART_CTL_RX, /* enable/disable receiver */
CUART_CTL_POWER, /* enable/disable ICC power */
CUART_CTL_CLOCK, /* enable/disable ICC clock */
CUART_CTL_CLOCK_FREQ, /* set ICC clock frequency (hz)*/
CUART_CTL_RST, /* enable/disable ICC reset */
CUART_CTL_WTIME, /* set the waiting time (in etu) */
CUART_CTL_FD,

View File

@ -290,7 +290,7 @@ static int asf4_usart_open(struct card_uart *cuart, const char *device_name)
cuart->u.asf4.slot_nr = slot_nr;
/* in us, 20Mhz with default ncn8025 divider 8, F=372, D=1*/
cuart->u.asf4.extrawait_after_rx = 1./(2./8/372);
cuart->u.asf4.extrawait_after_rx = 1./(20./8/372);
usart_async_register_callback(usa_pd, USART_ASYNC_RXC_CB, SIM_rx_cb[slot_nr]);
usart_async_register_callback(usa_pd, USART_ASYNC_TXC_CB, SIM_tx_cb[slot_nr]);
@ -366,7 +366,7 @@ static int asf4_usart_ctrl(struct card_uart *cuart, enum card_uart_ctl ctl, int
break;
case CUART_CTL_POWER:
/* in us, 20Mhz with default ncn8025 divider 8, F=372, D=1*/
cuart->u.asf4.extrawait_after_rx = 1./(2./8/372);
cuart->u.asf4.extrawait_after_rx = 1./(20./8/372);
// set USART baud rate to match the interface (f = 2.5 MHz) and card default settings (Fd = 372, Dd = 1)
if(arg)
@ -383,15 +383,18 @@ static int asf4_usart_ctrl(struct card_uart *cuart, enum card_uart_ctl ctl, int
/* no driver-specific handling of this */
break;
case CUART_CTL_CLOCK:
/* no clock stop support */
break;
case CUART_CTL_CLOCK_FREQ:
ncn8025_get(cuart->u.asf4.slot_nr, &settings);
/* 2,5/5/10/20 supported by dividers */
enum ncn8025_sim_clkdiv clkdiv = SIM_CLKDIV_1;
if(arg < 20)
if(arg < 20000000)
clkdiv = SIM_CLKDIV_2;
if(arg < 10)
if(arg < 10000000)
clkdiv = SIM_CLKDIV_4;
if(arg < 5)
if(arg < 5000000)
clkdiv = SIM_CLKDIV_8;
settings.clkdiv = clkdiv;
ncn8025_set(cuart->u.asf4.slot_nr, &settings);