166 lines
3.7 KiB
C
166 lines
3.7 KiB
C
/* AT91SAM7 PWM routines for OpenPCD / OpenPICC
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*
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* (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
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*
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*/
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#include <lib_AT91SAM7.h>
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#include <AT91SAM7.h>
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#include <sys/types.h>
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#include <errno.h>
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#include <openpcd.h>
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#include <os/usb_handler.h>
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#include <os/pcd_enumerate.h>
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#include <os/req_ctx.h>
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#include <os/dbgu.h>
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#include "../openpcd.h"
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#define Hz
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#define kHz *1000 Hz
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#define MHz *1000 kHz
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#define MCLK (48 MHz)
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#if 1
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#define DEBUGPWM DEBUGPCRF
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#else
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#define DEBUGPWM(x, args...)
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#endif
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static AT91PS_PWMC pwm = AT91C_BASE_PWMC;
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/* find highest bit set. returns bit (32..1) or 0 in case no bit set */
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static int fhs(u_int32_t val)
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{
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int i;
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for (i = 32; i > 0; i--) {
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if (val & (1 << (i-1)))
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return i;
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}
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return 0;
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}
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/* set frequency of PWM signal to freq */
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int pwm_freq_set(int channel, u_int32_t freq)
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{
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/* in order to get maximum resolution, the pre-scaler must be set to
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* something like freq << 16. However, the mimimum pre-scaled frequency
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* we can get is MCLK (48MHz), the minimum is MCLK/(1024*255) =
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* 48MHz/261120 = 183Hz */
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u_int32_t overall_div;
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u_int32_t presc_total;
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u_int8_t cpre = 0;
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u_int16_t cprd;
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if (freq > MCLK)
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return -ERANGE;
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overall_div = MCLK / freq;
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DEBUGPCRF("mclk=%u, freq=%u, overall_div=%u", MCLK, freq, overall_div);
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if (overall_div > 0x7fff) {
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/* divisor is larger than half the maximum CPRD register, we
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* have to configure prescalers */
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presc_total = overall_div >> 15;
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/* find highest 2^n fitting in prescaler (highest bit set) */
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cpre = fhs(presc_total);
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if (cpre > 0) {
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/* subtract one, because of fhs semantics */
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cpre--;
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}
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cprd = overall_div / (1 << cpre);
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} else
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cprd = overall_div;
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DEBUGPCRF("cpre=%u, cprd=%u", cpre, cprd);
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AT91F_PWMC_CfgChannel(AT91C_BASE_PWMC, channel,
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cpre|AT91C_PWMC_CPOL, cprd, 1);
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return 0;
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}
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void pwm_start(int channel)
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{
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AT91F_PWMC_StartChannel(AT91C_BASE_PWMC, (1 << channel));
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}
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void pwm_stop(int channel)
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{
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AT91F_PWMC_StopChannel(AT91C_BASE_PWMC, (1 << channel));
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}
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void pwm_duty_set_percent(int channel, u_int16_t duty)
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{
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u_int32_t tmp = pwm->PWMC_CH[channel].PWMC_CPRDR & 0xffff;
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tmp = tmp << 16; /* extend value by 2^16 */
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tmp = tmp / 100; /* tmp = 1 % of extended cprd */
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tmp = duty * tmp; /* tmp = 'duty' % of extended cprd */
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tmp = tmp >> 16; /* un-extend tmp (divide by 2^16) */
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DEBUGPWM("Writing %u to Update register\n", tmp);
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AT91F_PWMC_UpdateChannel(AT91C_BASE_PWMC, channel, tmp);
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}
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static int pwm_usb_in(struct req_ctx *rctx)
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{
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struct openpcd_hdr *poh = (struct openpcd_hdr *) &rctx->rx.data[0];
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/* struct openpcd_hdr *pih = (struct openpcd_hdr *) &rctx->tx.data[0]; */
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u_int32_t *freq;
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switch (poh->cmd) {
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case OPENPCD_CMD_PWM_ENABLE:
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if (poh->val)
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pwm_start(0);
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else
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pwm_stop(0);
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break;
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case OPENPCD_CMD_PWM_DUTY_SET:
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pwm_duty_set_percent(0, poh->val);
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break;
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case OPENPCD_CMD_PWM_DUTY_GET:
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goto respond;
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break;
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case OPENPCD_CMD_PWM_FREQ_SET:
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if (rctx->rx.tot_len < sizeof(*poh)+4)
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break;
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freq = (unsigned char *) poh + sizeof(*poh);
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pwm_freq_set(0, *freq);
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break;
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case OPENPCD_CMD_PWM_FREQ_GET:
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goto respond;
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break;
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default:
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break;
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}
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req_ctx_put(rctx);
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return 0;
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respond:
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req_ctx_set_state(rctx, RCTX_STATE_UDP_EP2_PENDING);
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udp_refill_ep(2, rctx);
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return 1;
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}
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void pwm_init(void)
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{
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/* IMPORTANT: Disable PA17 (SSC TD) output */
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AT91F_PIO_CfgInput(AT91C_BASE_PIOA, AT91C_PIO_PA17);
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/* Set PA23 to Peripheral A (PWM0) */
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AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, OPENPCD_PIO_MFIN_PWM);
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/* Enable Clock for PWM controller */
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AT91F_PWMC_CfgPMC();
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usb_hdlr_register(&pwm_usb_in, OPENPCD_CMD_CLS_PWM);
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}
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void pwm_fini(void)
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{
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usb_hdlr_unregister(OPENPCD_CMD_CLS_PWM);
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AT91F_PMC_DisablePeriphClock(AT91C_BASE_PMC, (1 << AT91C_ID_PWMC));
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}
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