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8 Commits

Author SHA1 Message Date
henryk 6304718e37 Port over the differential miller decoder from the sniffonly host tool 
Move clock switch to its own header file
Specify default (and for non-clock switching capable hardware: single) clock source in hardware definitions


git-svn-id: https://svn.openpcd.org:2342/trunk@443 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
 2008-03-05 05:03:36 +00:00
henryk ad5b96d584 New cleaned-up (and then messed up again) SSC code 
Better layering separation


git-svn-id: https://svn.openpcd.org:2342/trunk@434 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
 2008-02-29 08:53:20 +00:00
henryk a2c6b650bf Optimizing (disabling debugging reduces time spent in decoder from 460us to 60us 
git-svn-id: https://svn.openpcd.org:2342/trunk@396 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
 2007-12-17 05:38:01 +00:00
henryk 7c198cbff3 Record size of SSC RX DMA buffers in transfers, much clearer 
Change miller decoder to take an RX DMA buffer in order to have access to the reception_mode member, much more versatile


git-svn-id: https://svn.openpcd.org:2342/trunk@393 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
 2007-12-15 20:56:57 +00:00
henryk 40bf6fbf1a Further the distinction between SSC and PDC transfersize 
Add convenient access to the last data bit from the miller decoder for type a frames


git-svn-id: https://svn.openpcd.org:2342/trunk@391 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
 2007-12-15 17:13:26 +00:00
henryk bcc75d30ce Fix consistency check 
Fix miller decoder for the case of a buffer containing only zeroes


git-svn-id: https://svn.openpcd.org:2342/trunk@388 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
 2007-12-15 12:52:35 +00:00
henryk 5a29168ead Sanitize and clarify the len handling in rx buffers. 
Fix miller decoder


git-svn-id: https://svn.openpcd.org:2342/trunk@387 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
 2007-12-14 23:13:20 +00:00
henryk 202b56a42c Add new miller decoder (not working yet) 
Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness)  in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction


git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
 2007-12-12 01:50:14 +00:00