Add new miller decoder (not working yet)
Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
This commit is contained in:
henryk
parent
3d0e1db9d1
commit
202b56a42c
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@ -90,6 +90,7 @@ ARM_SRC= \
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application/usb_print.c \
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application/iso14443_layer3a.c \
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application/iso14443a_manchester.c \
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application/iso14443a_miller.c \
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application/load_modulation.c \
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application/decoder_miller.c \
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application/decoder_nrzl.c \
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@ -37,13 +37,14 @@
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#include "load_modulation.h"
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#include "decoder.h"
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#include "iso14443a_manchester.h"
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#include "iso14443a_miller.h"
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#include "led.h"
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static enum ISO14443_STATES state = STARTING_UP;
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const iso14443_frame ATQA_FRAME = {
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TYPE_A,
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{{STANDARD_FRAME, PARITY}},
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2,
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2,
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0, 0,
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{4, 0},
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{}
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@ -85,11 +86,11 @@ const iso14443_frame NULL_FRAME = {
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void iso14443_transmit(ssc_dma_tx_buffer_t *buf, int fdt, int div)
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{
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tc_cdiv_set_divider(div);
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if(fdt == ISO14443A_TRANSMIT_AT_NEXT_INTERVAL_0 ||
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fdt == ISO14443A_TRANSMIT_AT_NEXT_INTERVAL_1) {
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/* FIXME Implement */
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return;
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}
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if(fdt == ISO14443A_TRANSMIT_AT_NEXT_INTERVAL_0) {
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fdt = tc_fdt_get_next_slot(ISO14443A_FDT_SHORT_0, ISO14443A_FDT_SLOTLEN);
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} else if (fdt == ISO14443A_TRANSMIT_AT_NEXT_INTERVAL_1) {
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fdt = tc_fdt_get_next_slot(ISO14443A_FDT_SHORT_1, ISO14443A_FDT_SLOTLEN);
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}
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ssc_tx_fiq_fdt_cdiv = fdt -3*div -1;
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tc_fdt_set(ssc_tx_fiq_fdt_cdiv -MAX_TF_FIQ_ENTRY_DELAY -MAX_TF_FIQ_OVERHEAD);
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ssc_tx_fiq_fdt_ssc = fdt -div +1;
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@ -162,7 +163,7 @@ static int prefill_buffer(ssc_dma_tx_buffer_t *dest, const iso14443_frame *src)
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}
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static u_int8_t received_buffer[256];
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static iso14443_frame received_frame;
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static void enable_reception(enum ssc_mode mode) {
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tc_fdt_set(0xff00);
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@ -307,6 +308,12 @@ void iso14443_layer3a_state_machine (void *pvParameters)
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LAYER3_DEBUG(", woke up to send ATQA\n\r");
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atqa_sent = 0;
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}
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if(1) {
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DumpStringToUSB("Decoded: ");
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iso14443a_decode_miller(&received_frame, buffer->data, buffer->len);
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DumpBufferToUSB((char*)received_frame.data, 100);
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DumpStringToUSB("\n\r");
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}
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/* For debugging, wait 1ms, then wait for another frame
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* Normally we'd go to anticol from here*/
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vTaskDelay(portTICK_RATE_MS);
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@ -320,12 +327,12 @@ void iso14443_layer3a_state_machine (void *pvParameters)
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break;
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case ACTIVE:
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case ACTIVE_STAR:
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if(0) {
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#if 0
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DumpStringToUSB("Decoded: ");
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decoder_decode(DECODER_MILLER, (const char*)buffer->data, buffer->len, received_buffer);
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DumpBufferToUSB((char*)received_buffer, 100);
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DumpStringToUSB("\n\r");
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}
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#endif
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/* Wait for another frame */
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if(0) {
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ssc_rx_mode_set(SSC_MODE_14443A_STANDARD);
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@ -336,7 +343,7 @@ void iso14443_layer3a_state_machine (void *pvParameters)
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if(prefill_buffer(&ssc_tx_buffer, &NULL_FRAME)) {
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usb_print_string_f("Sending response ...",0);
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ssc_tx_buffer.state = PROCESSING;
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iso14443_transmit(&ssc_tx_buffer, 1, 8);
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iso14443_transmit(&ssc_tx_buffer, ISO14443A_TRANSMIT_AT_NEXT_INTERVAL_1, 8);
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while( ssc_tx_buffer.state != FREE ) {
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vTaskDelay(portTICK_RATE_MS);
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}
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@ -16,21 +16,6 @@ enum ISO14443_STATES {
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};
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/******************** RX ************************************/
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/* Magic delay, don't know where it comes from */
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#define MAGIC_OFFSET -32
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/* Delay from modulation till detection in SSC_DATA */
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#define DETECTION_DELAY 11
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/* See fdt_timinig.dia for these values */
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#define MAX_TF_FIQ_ENTRY_DELAY 16
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#define MAX_TF_FIQ_OVERHEAD 75 /* guesstimate */
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extern volatile int fdt_offset;
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/* standard derived magic values */
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#define ISO14443A_FDT_SLOTLEN 128
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#define ISO14443A_FDT_OFFSET_1 84
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#define ISO14443A_FDT_OFFSET_0 20
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#define ISO14443A_FDT_SHORT_1 (ISO14443A_FDT_SLOTLEN*9 + ISO14443A_FDT_OFFSET_1 +fdt_offset +MAGIC_OFFSET -DETECTION_DELAY)
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#define ISO14443A_FDT_SHORT_0 (ISO14443A_FDT_SLOTLEN*9 + ISO14443A_FDT_OFFSET_0 +fdt_offset +MAGIC_OFFSET -DETECTION_DELAY)
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#ifdef FOUR_TIMES_OVERSAMPLING
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/* definitions for four-times oversampling */
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/* Sample values for the REQA and WUPA short frames */
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@ -82,6 +67,21 @@ extern volatile int fdt_offset;
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#endif
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/******************** TX ************************************/
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/* Magic delay, don't know where it comes from */
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#define MAGIC_OFFSET -32
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/* Delay from modulation till detection in SSC_DATA */
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#define DETECTION_DELAY 11
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/* See fdt_timinig.dia for these values */
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#define MAX_TF_FIQ_ENTRY_DELAY 16
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#define MAX_TF_FIQ_OVERHEAD 75 /* guesstimate */
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extern volatile int fdt_offset;
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/* standard derived magic values */
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#define ISO14443A_FDT_SLOTLEN 128
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#define ISO14443A_FDT_OFFSET_1 84
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#define ISO14443A_FDT_OFFSET_0 20
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#define ISO14443A_FDT_SHORT_1 (ISO14443A_FDT_SLOTLEN*9 + ISO14443A_FDT_OFFSET_1 +fdt_offset +MAGIC_OFFSET -DETECTION_DELAY)
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#define ISO14443A_FDT_SHORT_0 (ISO14443A_FDT_SLOTLEN*9 + ISO14443A_FDT_OFFSET_0 +fdt_offset +MAGIC_OFFSET -DETECTION_DELAY)
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/* in bytes, not counting parity */
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#define MAXIMUM_FRAME_SIZE 256
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@ -1,5 +1,6 @@
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/* ISO14443A Manchester encoder for OpenPICC
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* (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
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* (C) 2007 by Henryk Plötz <henryk@ploetzli.ch>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -0,0 +1,112 @@
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/* ISO14443A Manchester encoder for OpenPICC
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* (C) 2007 by Henryk Plötz <henryk@ploetzli.ch>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <openpicc.h>
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#include <FreeRTOS.h>
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#include <string.h>
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#include "iso14443_layer3a.h"
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#include "usb_print.h"
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#include "cmd.h"
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#ifdef FOUR_TIMES_OVERSAMPLING
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#define OVERSAMPLING_RATE 4
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/* definitions for four-times oversampling */
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#define SEQ_X 0x4
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#define SEQ_Y 0x0
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#define SEQ_Z 0x1
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#else
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#define OVERSAMPLING_RATE 2
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#define SEQ_X 0x2
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#define SEQ_Y 0x0
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#define SEQ_Z 0x1
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#endif
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enum miller_sequence {
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SEQUENCE_X,
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SEQUENCE_Y,
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SEQUENCE_Z,
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};
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#define BIT_ENDMARKER -1
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int iso14443a_decode_miller(iso14443_frame *frame,
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const u_int8_t *sample_buf, const u_int16_t sample_buf_len)
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{
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signed int i, j, bit = 0, last_bit = 0;
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enum miller_sequence current_seq;
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unsigned int bitpos = 0;
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memset(frame, 0, sizeof(frame));
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frame->type = TYPE_A;
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frame->parameters.a.parity = GIVEN_PARITY;
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for(i=0; i<sample_buf_len && bit != BIT_ENDMARKER; i++) {
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for(j=0; j<(signed)(sizeof(sample_buf[0])*8)/OVERSAMPLING_RATE && bit != BIT_ENDMARKER; j++) {
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int sample = (sample_buf[i]>>(j*OVERSAMPLING_RATE)) & ~(~0 << OVERSAMPLING_RATE);
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switch(sample) {
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case SEQ_X: current_seq = SEQUENCE_X; break;
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case SEQ_Y: current_seq = SEQUENCE_Y; break;
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case SEQ_Z: current_seq = SEQUENCE_Z; break;
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default: current_seq = SEQUENCE_Y;
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}
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switch(current_seq) {
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case SEQ_X:
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DumpStringToUSB("X");
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bit = 1; break;
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case SEQ_Y: /* Fall-through to SEQ_Z */
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DumpStringToUSB("Y");
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if(last_bit == 0) {
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bit = BIT_ENDMARKER;
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break;
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}
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case SEQ_Z:
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DumpStringToUSB("Z");
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bit = 0; break;
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}
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switch(bit) {
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case BIT_ENDMARKER:
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bitpos--;
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break;
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case 0: /* Fall-through */
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case 1: {
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int bytepos = bitpos/9;
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if(bitpos % 9 == 8) { /* Parity bit */
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frame->parity[ bytepos/8 ] |= (bit<<(bytepos%8));
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} else {
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frame->data[ bytepos ] |= (bit<<(bitpos%9));
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}
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}
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}
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last_bit = bit;
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bitpos++;
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}
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}
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frame->numbytes = bitpos/9;
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frame->numbits = bitpos%9;
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DumpStringToUSB("\n\r");
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return 0;
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}
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@ -0,0 +1,6 @@
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#ifndef ISO14443A_MILLER_H_
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#define ISO14443A_MILLER_H_
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extern int iso14443a_decode_miller(iso14443_frame *frame, const u_int8_t *sample_buf, const u_int16_t sample_buf_len);
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#endif /*ISO14443A_MILLER_H_*/
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@ -50,16 +50,12 @@ void tc_fdt_set(u_int16_t count)
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tcfdt->TC_RA = count;
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}
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void __ramfunc tc_fdt_set_to_next_slot(int last_bit)
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int tc_fdt_get_next_slot(int reference_time, int slotlen)
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{
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int reference_time;
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if(last_bit == 0) reference_time = ISO14443A_FDT_OFFSET_0;
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else reference_time = ISO14443A_FDT_OFFSET_1;
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if(tcfdt->TC_SR & AT91C_TC_CLKSTA)
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/*if(tcfdt->TC_SR & AT91C_TC_CLKSTA)
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while(tcfdt->TC_CV != 0xFFFF && (tcfdt->TC_CV - reference_time) % 128 != 0);
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tcfdt->TC_CCR = AT91C_TC_SWTRG;
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tc_fdt_set(2*128);
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tcfdt->TC_CCR = AT91C_TC_SWTRG;*/
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return tcfdt->TC_CV + (slotlen-((tcfdt->TC_CV - reference_time) % slotlen)) + 3*slotlen;
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}
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@ -5,6 +5,6 @@
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extern void tc_fdt_init(void);
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extern void tc_fdt_set(u_int16_t count);
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extern void __ramfunc tc_fdt_set_to_next_slot(int last_bit);
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extern int tc_fdt_get_next_slot(int reference_time, int slotlen);
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#endif
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@ -250,10 +250,39 @@ my_fiq_handler:
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ldr r11, =ssc_tx_fiq_fdt_cdiv
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ldr r11, [r11] /* r11 == ssc_tx_fiq_fdt_cdiv */
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/* Problem: LDR from the timer still takes too long and causes us to miss the exact time.
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* Strategy: Spin on TC2 till we are very near the actual time. Then load the timer value, calculate
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* the difference to the target, then do a countdown spin without reading the timer.
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*
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* At 47.923200 MHz 7 processor cycles are 2 carrier cycles of the 13.56MHz carrier
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*/
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.equ SUB_TIME, 20 /* subtract 20 carrier cycles == 70 processor cycles */
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.equ ADD_TIME, (70-20) /* Add x processor cycles */
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mov r8, #SUB_TIME
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sub r11, r11, r8
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.wait_for_fdt_cdiv:
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ldr r8, [r12, #TC2_CV]
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cmp r8, r11
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bmi .wait_for_fdt_cdiv /* spin while TC2.CV is less fdt_cdiv */
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bmi .wait_for_fdt_cdiv /* spin while TC2.CV is less fdt_cdiv-SUB_TIM */
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ldr r8, [r12, #TC2_CV]
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sub r11, r11, r8 /* r11 == fdt_cdiv-SUB_TIME - TC2.CV */
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mov r8, #0x07
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mul r11, r8, r11 /* r11 = r11 * 7 */
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mov r11, r11, ASR #1 /* r11 = r11 / 2 */
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mov r8, #ADD_TIME
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add r11, r11, r8 /* r11 = r11 + ADD_TIME */
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mov r11, r11, ASR #2 /* r11 = r11 / 4 (4 is the number of cycles per loop run below) */
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mov r8, #1
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.wait_for_my_time:
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subs r11, r11, r8
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bge .wait_for_my_time
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str r9, [r12, #TC_CCR] /* SWTRG on TC0 */
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