tuner_fc0012: use new cleaned-up driver
The driver was taken from http://git.linuxtv.org/ and adapted for librtlsdr. Manual gain will be added in a follow-up commit. Signed-off-by: Steve Markgraf <steve@steve-m.de>
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@ -1,25 +1,36 @@
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#ifndef __TUNER_FC0012_H
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#define __TUNER_FC0012_H
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/*
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* Fitipower FC0012 tuner driver
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*
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* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
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*
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* modified for use in librtlsdr
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* Copyright (C) 2012 Steve Markgraf <steve@steve-m.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#define FC0012_OK 0
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#define FC0012_ERROR 1
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#ifndef _FC0012_H_
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#define _FC0012_H_
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#define FC0012_I2C_ADDR 0xc6
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#define FC0012_CHECK_ADDR 0x00
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#define FC0012_CHECK_VAL 0xa1
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#define FC0012_BANDWIDTH_6MHZ 6
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#define FC0012_BANDWIDTH_7MHZ 7
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#define FC0012_BANDWIDTH_8MHZ 8
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#define FC0012_LNA_GAIN_LOW 0x00
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#define FC0012_LNA_GAIN_MID 0x08
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#define FC0012_LNA_GAIN_HI 0x17
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#define FC0012_LNA_GAIN_MAX 0x10
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int FC0012_Open(void *pTuner);
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int FC0012_Read(void *pTuner, unsigned char RegAddr, unsigned char *pByte);
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int FC0012_Write(void *pTuner, unsigned char RegAddr, unsigned char Byte);
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int FC0012_SetFrequency(void *pTuner, unsigned long Frequency, unsigned short Bandwidth);
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int fc0012_init(void *dev);
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int fc0012_set_params(void *dev, uint32_t freq, uint32_t bandwidth);
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int fc0012_set_gain(void *dev, int gain);
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#endif
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@ -122,17 +122,17 @@ int e4000_set_gain_mode(void *dev, int manual) {
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return 0;
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}
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int fc0012_init(void *dev) { return FC0012_Open(dev); }
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int _fc0012_init(void *dev) { return fc0012_init(dev); }
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int fc0012_exit(void *dev) { return 0; }
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int fc0012_set_freq(void *dev, uint32_t freq) {
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/* select V-band/U-band filter */
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rtlsdr_set_gpio_bit(dev, 6, (freq > 300000000) ? 1 : 0);
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return FC0012_SetFrequency(dev, freq/1000, 6);
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return fc0012_set_params(dev, freq, 6000000);
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}
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int fc0012_set_bw(void *dev, int bw) {
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return FC0012_SetFrequency(dev, ((rtlsdr_dev_t *) dev)->freq/1000, 6);
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int fc0012_set_bw(void *dev, int bw) { return 0; }
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int _fc0012_set_gain(void *dev, int gain) {
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return fc0012_set_gain(dev, gain);
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}
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int fc0012_set_gain(void *dev, int gain) { return 0; }
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int fc0012_set_gain_mode(void *dev, int manual) { return 0; }
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int _fc0013_init(void *dev) { return fc0013_init(dev); }
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@ -173,8 +173,8 @@ static rtlsdr_tuner_t tuners[] = {
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e4000_set_gain_mode
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},
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{
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fc0012_init, fc0012_exit,
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fc0012_set_freq, fc0012_set_bw, fc0012_set_gain,
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_fc0012_init, fc0012_exit,
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fc0012_set_freq, fc0012_set_bw, _fc0012_set_gain,
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fc0012_set_gain_mode
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},
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{
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@ -1,21 +1,57 @@
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/*
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* fc0012 tuner support for rtl-sdr
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* Fitipower FC0012 tuner driver
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*
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* Based on tuner_fc0012.c found as part of the (seemingly GPLed)
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* rtl2832u Linux DVB driver.
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* Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
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*
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* Rewritten and hacked into rtl-sdr by David Basden <davidb-sdr@rcpt.to>
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* modified for use in librtlsdr
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* Copyright (C) 2012 Steve Markgraf <steve@steve-m.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include "rtlsdr_i2c.h"
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#include "tuner_fc0012.h"
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#define CRYSTAL_FREQ 28800000
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static int fc0012_writereg(void *dev, uint8_t reg, uint8_t val)
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{
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uint8_t data[2];
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data[0] = reg;
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data[1] = val;
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#define FC0012_LNAGAIN FC0012_LNA_GAIN_HI
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if (rtlsdr_i2c_write_fn(dev, FC0012_I2C_ADDR, data, 2) < 0)
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return -1;
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return 0;
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}
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static int fc0012_readreg(void *dev, uint8_t reg, uint8_t *val)
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{
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uint8_t data = reg;
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if (rtlsdr_i2c_write_fn(dev, FC0012_I2C_ADDR, &data, 1) < 0)
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return -1;
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if (rtlsdr_i2c_read_fn(dev, FC0012_I2C_ADDR, &data, 1) < 0)
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return -1;
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*val = data;
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return 0;
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}
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/* Incomplete list of register settings:
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*
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@ -30,7 +66,7 @@
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* RF_OUTDIV_A 0x05 3-7 Power of two required?
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* LNA_POWER_DOWN 0x06 0 Set to 1 to switch off low noise amp
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* RF_OUTDIV_B 0x06 1 Set to select 3 instead of 2 for the
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* RF output divider
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* RF output divider
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* VCO_SPEED 0x06 3 Select tuning range of VCO:
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* 0 = Low range, (ca. 1.1 - 1.5GHz)
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* 1 = High range (ca. 1.4 - 1.8GHz)
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@ -51,277 +87,226 @@
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* (big value -> low freq)
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*/
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/* glue functions to rtl-sdr code */
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int FC0012_Write(void *pTuner, unsigned char RegAddr, unsigned char Byte)
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int fc0012_init(void *dev)
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{
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uint8_t data[2];
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int ret = 0;
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unsigned int i;
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uint8_t reg[] = {
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0x00, /* dummy reg. 0 */
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0x05, /* reg. 0x01 */
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0x10, /* reg. 0x02 */
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0x00, /* reg. 0x03 */
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0x00, /* reg. 0x04 */
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0x0f, /* reg. 0x05: may also be 0x0a */
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0x00, /* reg. 0x06: divider 2, VCO slow */
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0x00, /* reg. 0x07: may also be 0x0f */
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0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
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Loop Bw 1/8 */
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0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */
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0xb8, /* reg. 0x0a: Disable LO Test Buffer */
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0x82, /* reg. 0x0b: Output Clock is same as clock frequency,
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may also be 0x83 */
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0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
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0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */
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0x00, /* reg. 0x0e */
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0x00, /* reg. 0x0f */
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0x00, /* reg. 0x10: may also be 0x0d */
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0x00, /* reg. 0x11 */
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0x1f, /* reg. 0x12: Set to maximum gain */
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0x08, /* reg. 0x13: Set to Middle Gain: 0x08,
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Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */
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0x00, /* reg. 0x14 */
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0x04, /* reg. 0x15: Enable LNA COMPS */
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};
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data[0] = RegAddr;
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data[1] = Byte;
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if (rtlsdr_i2c_write_fn(pTuner, FC0012_I2C_ADDR, data, 2) < 0)
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return FC0012_ERROR;
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return FC0012_OK;
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}
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int FC0012_Read(void *pTuner, unsigned char RegAddr, unsigned char *pByte)
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{
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uint8_t data = RegAddr;
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if (rtlsdr_i2c_write_fn(pTuner, FC0012_I2C_ADDR, &data, 1) < 0)
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return FC0012_ERROR;
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if (rtlsdr_i2c_read_fn(pTuner, FC0012_I2C_ADDR, &data, 1) < 0)
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return FC0012_ERROR;
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*pByte = data;
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return FC0012_OK;
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}
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#ifdef DEBUG
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#define DEBUGF printf
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#else
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#define DEBUGF(...) ()
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#endif
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#if 0
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void FC0012_Dump_Registers()
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{
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#ifdef DEBUG
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unsigned char regBuf;
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int ret;
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int i;
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DEBUGF("\nFC0012 registers:\n");
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for (i=0; i<=0x15; ++i)
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{
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ret = FC0012_Read(pTuner, i, ®Buf);
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if (ret) DEBUGF("\nCouldn't read register %02x\n", i);
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DEBUGF("R%x=%02x ",i,regBuf);
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}
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DEBUGF("\n");
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FC0012_Read(pTuner, 0x06, ®Buf);
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DEBUGF("LNA_POWER_DOWN:\t%s\n", regBuf & 1 ? "Powered down" : "Not Powered Down");
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DEBUGF("VCO_SPEED:\t%s\n", regBuf & 0x8 ? "High speed" : "Slow speed");
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DEBUGF("Bandwidth:\t%s\n", (regBuf & 0xC) ? "8MHz" : "less than 8MHz");
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FC0012_Read(pTuner, 0x07, ®Buf);
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DEBUGF("Crystal Speed:\t%s\n", (regBuf & 0x20) ? "28.8MHz" : "36MHZ<!>");
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FC0012_Read(pTuner, 0x09, ®Buf);
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DEBUGF("RSSI calibration mode:\t%s\n", (regBuf & 0x10) ? "RSSI CALIBRATION IN PROGRESS<!>" : "Disabled");
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FC0012_Read(pTuner, 0x0d, ®Buf);
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DEBUGF("LNA Force:\t%s\n", (regBuf & 0x1) ? "Forced" : "Not Forced");
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FC0012_Read(pTuner, 0x13, ®Buf);
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DEBUGF("LNA Gain:\t");
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switch (regBuf & 0x18) {
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case (0x00): DEBUGF("Low\n"); break;
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case (0x08): DEBUGF("Middle\n"); break;
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case (0x10): DEBUGF("High\n"); break;
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default: DEBUGF("unknown gain value 0x18\n");
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switch (rtlsdr_get_tuner_clock(dev)) {
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case FC_XTAL_27_MHZ:
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case FC_XTAL_28_8_MHZ:
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reg[0x07] |= 0x20;
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break;
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case FC_XTAL_36_MHZ:
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default:
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break;
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}
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#endif
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}
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#endif
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reg[0x07] |= 0x20;
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int FC0012_Open(void *pTuner)
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{
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// DEBUGF("FC0012_Open start");
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if (FC0012_Write(pTuner, 0x01, 0x05)) return -1;
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if (FC0012_Write(pTuner, 0x02, 0x10)) return -1;
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if (FC0012_Write(pTuner, 0x03, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x04, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x05, 0x0F)) return -1;
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if (FC0012_Write(pTuner, 0x06, 0x00)) return -1; // divider 2, VCO slow
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if (FC0012_Write(pTuner, 0x07, 0x20)) return -1; // change to 0x00 for a 36MHz crystal
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if (FC0012_Write(pTuner, 0x08, 0xFF)) return -1; // AGC Clock divide by 254, AGC gain 1/256, Loop Bw 1/8
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if (FC0012_Write(pTuner, 0x09, 0x6E)) return -1; // Disable LoopThrough
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if (FC0012_Write(pTuner, 0x0A, 0xB8)) return -1; // Disable LO Test Buffer
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if (FC0012_Write(pTuner, 0x0B, 0x82)) return -1; // Output Clock is same as clock frequency
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//if (FC0012_Write(pTuner, 0x0C, 0xF8)) return -1;
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if (FC0012_Write(pTuner, 0x0C, 0xFC)) return -1; // AGC up-down mode
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if (FC0012_Write(pTuner, 0x0D, 0x02)) return -1; // AGC Not Forcing & LNA Forcing
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if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x0F, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x10, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x11, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x12, 0x1F)) return -1; // Set to maximum gain
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if (FC0012_Write(pTuner, 0x13, FC0012_LNAGAIN)) return -1;
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if (FC0012_Write(pTuner, 0x14, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x15, 0x04)) return -1; // Enable LNA COMPS
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// if (priv->dual_master)
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reg[0x0c] |= 0x02;
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/* Black magic from nim_rtl2832_fc0012.c in DVB driver.
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Even though we've set 0x11 to 0x00 above, this needs to happen to have
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it go back
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*/
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if (FC0012_Write(pTuner, 0x0d, 0x02)) return -1;
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if (FC0012_Write(pTuner, 0x11, 0x00)) return -1;
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if (FC0012_Write(pTuner, 0x15, 0x04)) return -1;
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for (i = 1; i < sizeof(reg); i++) {
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ret = fc0012_writereg(dev, i, reg[i]);
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if (ret)
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break;
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}
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// DEBUGF("FC0012_Open SUCCESS");
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return FC0012_OK;
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return ret;
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}
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# if 0
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// Frequency is in kHz. Bandwidth is in MHz
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// This is pseudocode to set GPIO6 for VHF/UHF filter switching.
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// Trying to do this in reality leads to fail currently. I'm probably doing it wrong.
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void FC0012_Frequency_Control(unsigned int Frequency, unsigned short Bandwidth)
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int fc0012_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
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{
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if( Frequency < 260000 && Frequency > 150000 )
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{
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// set GPIO6 = low
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int i, ret = 0;
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uint8_t reg[7], am, pm, multi, tmp;
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uint64_t f_vco;
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uint32_t xtal_freq_div_2;
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uint16_t xin, xdiv;
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int vco_select = 0;
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// 1. Set tuner frequency
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// 2. if the program quality is not good enough, switch to frequency + 500kHz
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// 3. if the program quality is still no good, switch to frequency - 500kHz
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}
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else
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{
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// set GPIO6 = high
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xtal_freq_div_2 = rtlsdr_get_tuner_clock(dev) / 2;
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// set tuner frequency
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}
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}
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#endif
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int FC0012_SetFrequency(void *pTuner, unsigned long Frequency, unsigned short Bandwidth)
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{
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int VCO_band = 0;
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unsigned long doubleVCO;
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unsigned short xin, xdiv;
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unsigned char reg[21], am, pm, multi;
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unsigned char read_byte;
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unsigned long CrystalFreqKhz;
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// DEBUGF("FC0012_SetFrequency start");
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CrystalFreqKhz = (rtlsdr_get_tuner_clock(pTuner) + 500) / 1000;
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//===================================== Select frequency divider and the frequency of VCO
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if (Frequency * 96 < 3560000)
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{
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multi = 96; reg[5] = 0x82; reg[6] = 0x00;
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}
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else if (Frequency * 64 < 3560000)
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{
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multi = 64; reg[5] = 0x82; reg[6] = 0x02;
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}
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else if (Frequency * 48 < 3560000)
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{
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multi = 48; reg[5] = 0x42; reg[6] = 0x00;
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}
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else if (Frequency * 32 < 3560000)
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{
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multi = 32; reg[5] = 0x42; reg[6] = 0x02;
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}
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else if (Frequency * 24 < 3560000)
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{
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multi = 24; reg[5] = 0x22; reg[6] = 0x00;
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}
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else if (Frequency * 16 < 3560000)
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{
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multi = 16; reg[5] = 0x22; reg[6] = 0x02;
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}
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else if (Frequency * 12 < 3560000)
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{
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multi = 12; reg[5] = 0x12; reg[6] = 0x00;
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}
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||||
else if (Frequency * 8 < 3560000)
|
||||
{
|
||||
multi = 8; reg[5] = 0x12; reg[6] = 0x02;
|
||||
}
|
||||
else if (Frequency * 6 < 3560000)
|
||||
{
|
||||
multi = 6; reg[5] = 0x0A; reg[6] = 0x00;
|
||||
}
|
||||
else
|
||||
{
|
||||
multi = 4; reg[5] = 0x0A; reg[6] = 0x02;
|
||||
}
|
||||
|
||||
doubleVCO = Frequency * multi;
|
||||
|
||||
reg[6] = reg[6] | 0x08;
|
||||
VCO_band = 1;
|
||||
xdiv = (unsigned short)(doubleVCO / (CrystalFreqKhz / 2));
|
||||
if( (doubleVCO - xdiv * (CrystalFreqKhz / 2)) >= (CrystalFreqKhz / 4) )
|
||||
xdiv = xdiv + 1;
|
||||
|
||||
pm = (unsigned char)( xdiv / 8 );
|
||||
am = (unsigned char)( xdiv - (8 * pm));
|
||||
|
||||
if (am < 2) {
|
||||
reg[1] = am + 8;
|
||||
reg[2] = pm - 1;
|
||||
/* select frequency divider and the frequency of VCO */
|
||||
if (freq < 37084000) { /* freq * 96 < 3560000000 */
|
||||
multi = 96;
|
||||
reg[5] = 0x82;
|
||||
reg[6] = 0x00;
|
||||
} else if (freq < 55625000) { /* freq * 64 < 3560000000 */
|
||||
multi = 64;
|
||||
reg[5] = 0x82;
|
||||
reg[6] = 0x02;
|
||||
} else if (freq < 74167000) { /* freq * 48 < 3560000000 */
|
||||
multi = 48;
|
||||
reg[5] = 0x42;
|
||||
reg[6] = 0x00;
|
||||
} else if (freq < 111250000) { /* freq * 32 < 3560000000 */
|
||||
multi = 32;
|
||||
reg[5] = 0x42;
|
||||
reg[6] = 0x02;
|
||||
} else if (freq < 148334000) { /* freq * 24 < 3560000000 */
|
||||
multi = 24;
|
||||
reg[5] = 0x22;
|
||||
reg[6] = 0x00;
|
||||
} else if (freq < 222500000) { /* freq * 16 < 3560000000 */
|
||||
multi = 16;
|
||||
reg[5] = 0x22;
|
||||
reg[6] = 0x02;
|
||||
} else if (freq < 296667000) { /* freq * 12 < 3560000000 */
|
||||
multi = 12;
|
||||
reg[5] = 0x12;
|
||||
reg[6] = 0x00;
|
||||
} else if (freq < 445000000) { /* freq * 8 < 3560000000 */
|
||||
multi = 8;
|
||||
reg[5] = 0x12;
|
||||
reg[6] = 0x02;
|
||||
} else if (freq < 593334000) { /* freq * 6 < 3560000000 */
|
||||
multi = 6;
|
||||
reg[5] = 0x0a;
|
||||
reg[6] = 0x00;
|
||||
} else {
|
||||
reg[1] = am;
|
||||
reg[2] = pm;
|
||||
multi = 4;
|
||||
reg[5] = 0x0a;
|
||||
reg[6] = 0x02;
|
||||
}
|
||||
|
||||
// From VCO frequency determines the XIN ( fractional part of Delta Sigma PLL) and divided value (XDIV).
|
||||
xin = (unsigned short)(doubleVCO - ((unsigned short)(doubleVCO / (CrystalFreqKhz / 2))) * (CrystalFreqKhz / 2));
|
||||
xin = ((xin << 15)/(unsigned short)(CrystalFreqKhz / 2));
|
||||
if( xin >= (unsigned short) 16384 )
|
||||
xin = xin + (unsigned short) 32768;
|
||||
f_vco = freq * multi;
|
||||
|
||||
reg[3] = (unsigned char)(xin >> 8);
|
||||
reg[4] = (unsigned char)(xin & 0x00FF);
|
||||
|
||||
// DEBUGF("Frequency: %lu, Fa: %d, Fp: %d, Xin:%d \n", Frequency, am, pm, xin);
|
||||
|
||||
switch(Bandwidth)
|
||||
{
|
||||
case 6: reg[6] = 0x80 | reg[6]; break;
|
||||
case 7: reg[6] = (~0x80 & reg[6]) | 0x40; break;
|
||||
case 8: default: reg[6] = ~0xC0 & reg[6]; break;
|
||||
if (f_vco >= 3060000000U) {
|
||||
reg[6] |= 0x08;
|
||||
vco_select = 1;
|
||||
}
|
||||
|
||||
if (FC0012_Write(pTuner, 0x01, reg[1])) return -1;
|
||||
if (FC0012_Write(pTuner, 0x02, reg[2])) return -1;
|
||||
if (FC0012_Write(pTuner, 0x03, reg[3])) return -1;
|
||||
if (FC0012_Write(pTuner, 0x04, reg[4])) return -1;
|
||||
//reg[5] = reg[5] | 0x07; // This is really not cool. Why is it there?
|
||||
if (FC0012_Write(pTuner, 0x05, reg[5])) return -1;
|
||||
if (FC0012_Write(pTuner, 0x06, reg[6])) return -1;
|
||||
if (freq >= 45000000) {
|
||||
/* From divided value (XDIV) determined the FA and FP value */
|
||||
xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
|
||||
if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
|
||||
xdiv++;
|
||||
|
||||
// VCO Calibration
|
||||
if (FC0012_Write(pTuner, 0x0E, 0x80)) return -1;
|
||||
if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
|
||||
pm = (uint8_t)(xdiv / 8);
|
||||
am = (uint8_t)(xdiv - (8 * pm));
|
||||
|
||||
// Read resulting VCO control voltage
|
||||
if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
|
||||
if (FC0012_Read(pTuner, 0x0E, &read_byte)) return -1;
|
||||
reg[14] = 0x3F & read_byte;
|
||||
|
||||
// Adjust VCO range if control voltage is at the limit
|
||||
if (VCO_band)
|
||||
{
|
||||
// high-band VCO hitting low frequency bound
|
||||
if (reg[14] > 0x3C)
|
||||
{
|
||||
// select low-band VCO
|
||||
reg[6] = ~0x08 & reg[6];
|
||||
|
||||
if (FC0012_Write(pTuner, 0x06, reg[6])) return -1;
|
||||
if (FC0012_Write(pTuner, 0x0E, 0x80)) return -1;
|
||||
if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
|
||||
if (am < 2) {
|
||||
reg[1] = am + 8;
|
||||
reg[2] = pm - 1;
|
||||
} else {
|
||||
reg[1] = am;
|
||||
reg[2] = pm;
|
||||
}
|
||||
} else {
|
||||
/* fix for frequency less than 45 MHz */
|
||||
reg[1] = 0x06;
|
||||
reg[2] = 0x11;
|
||||
}
|
||||
else
|
||||
{
|
||||
// low-band VCO hitting high frequency bound
|
||||
if (reg[14] < 0x02) {
|
||||
// select high-band VCO
|
||||
reg[6] = 0x08 | reg[6];
|
||||
|
||||
if (FC0012_Write(pTuner, 0x06, reg[6])) return -1;
|
||||
if (FC0012_Write(pTuner, 0x0E, 0x80)) return -1;
|
||||
if (FC0012_Write(pTuner, 0x0E, 0x00)) return -1;
|
||||
/* fix clock out */
|
||||
reg[6] |= 0x20;
|
||||
|
||||
/* From VCO frequency determines the XIN ( fractional part of Delta
|
||||
Sigma PLL) and divided value (XDIV) */
|
||||
xin = (uint16_t)((f_vco - (f_vco / xtal_freq_div_2) * xtal_freq_div_2) / 1000);
|
||||
xin = (xin << 15) / (xtal_freq_div_2 / 1000);
|
||||
if (xin >= 16384)
|
||||
xin += 32768;
|
||||
|
||||
reg[3] = xin >> 8; /* xin with 9 bit resolution */
|
||||
reg[4] = xin & 0xff;
|
||||
|
||||
reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
|
||||
switch (bandwidth) {
|
||||
case 6000000:
|
||||
reg[6] |= 0x80;
|
||||
break;
|
||||
case 7000000:
|
||||
reg[6] |= 0x40;
|
||||
break;
|
||||
case 8000000:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* modified for Realtek demod */
|
||||
reg[5] |= 0x07;
|
||||
|
||||
for (i = 1; i <= 6; i++) {
|
||||
ret = fc0012_writereg(dev, i, reg[i]);
|
||||
if (ret)
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* VCO Calibration */
|
||||
ret = fc0012_writereg(dev, 0x0e, 0x80);
|
||||
if (!ret)
|
||||
ret = fc0012_writereg(dev, 0x0e, 0x00);
|
||||
|
||||
/* VCO Re-Calibration if needed */
|
||||
if (!ret)
|
||||
ret = fc0012_writereg(dev, 0x0e, 0x00);
|
||||
|
||||
if (!ret) {
|
||||
// msleep(10);
|
||||
ret = fc0012_readreg(dev, 0x0e, &tmp);
|
||||
}
|
||||
if (ret)
|
||||
goto exit;
|
||||
|
||||
/* vco selection */
|
||||
tmp &= 0x3f;
|
||||
|
||||
if (vco_select) {
|
||||
if (tmp > 0x3c) {
|
||||
reg[6] &= ~0x08;
|
||||
ret = fc0012_writereg(dev, 0x06, reg[6]);
|
||||
if (!ret)
|
||||
ret = fc0012_writereg(dev, 0x0e, 0x80);
|
||||
if (!ret)
|
||||
ret = fc0012_writereg(dev, 0x0e, 0x00);
|
||||
}
|
||||
} else {
|
||||
if (tmp < 0x02) {
|
||||
reg[6] |= 0x08;
|
||||
ret = fc0012_writereg(dev, 0x06, reg[6]);
|
||||
if (!ret)
|
||||
ret = fc0012_writereg(dev, 0x0e, 0x80);
|
||||
if (!ret)
|
||||
ret = fc0012_writereg(dev, 0x0e, 0x00);
|
||||
}
|
||||
}
|
||||
|
||||
// DEBUGF("FC0012_SetFrequency SUCCESS"); FC0012_Dump_Registers();
|
||||
return FC0012_OK;
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fc0012_set_gain(void *dev, int gain)
|
||||
{
|
||||
/* TODO add gain regulation */
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue