150 lines
3.3 KiB
Plaintext
150 lines
3.3 KiB
Plaintext
[Project]
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Current Flow=Generic
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VCS=0
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version=3
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Current Config=compile
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[Configurations]
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compile=usbrx_vhdl
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[Library]
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usbrx_vhdl=.\usbrx_vhdl.LIB
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[Settings]
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AccessRead=0
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AccessReadWrite=0
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AccessACCB=0
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AccessACCR=0
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AccessReadWriteSLP=0
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AccessReadTopLevel=1
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DisableC=1
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ENABLE_ADV_DATAFLOW=0
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FLOW_TYPE=HDL
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LANGUAGE=VHDL
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REFRESH_FLOW=1
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FAMILY=Lattice XP2
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fileopeninsrc=1
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fileopenfolder=C:\
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IMPL_TOOL=
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SYNTH_TOOL=
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NoWarningsSDF=0
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SDFErrorLimit=0
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EnableSDFErrorLimit=0
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ChangeSDFErrorToWarning=0
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NoTchkMsg=0
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NoTimingChecks=0
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HESPrepare=0
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EnableXtrace=0
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SplitNetVectors=0
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StackMemorySize=32
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RetvalMemorySize=32
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VsimAdditionalOptions=
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DisableVitalMsg=0
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VitalAccel=1
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VitalGlitches=0
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DisableIEEEWarnings=0
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[LocalVerilogSets]
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EnableSLP=1
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EnableDebug=0
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[LocalVhdlSets]
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CompileWithDebug=1
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DisableVHDL87Key=0
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EnableVHDL93Key=0
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EnableVHDL2002Key=1
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EnableVHDL2006Key=0
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EnableVHDL2008Key=0
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NetlistCompilation=1
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Syntax RelaxLRM=0
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MaxErrorsKey=100
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OptimizationLevel=3
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DisableRangeChecks=0
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ProtectLevel=0
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AdditionalOptions=
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IncrementalCompilation=0
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[$LibMap$]
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usbrx_vhdl=.
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Active_lib=
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[HierarchyViewer]
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SortInfo=u
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HierarchyInformation=
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ShowHide=ShowTopLevel
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Selected=
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[Folders]
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Name3=Makefiles
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Directory3=C:\
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Extension3=mak
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Name4=Memory
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Directory4=C:\
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Extension4=mem;mif;hex
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Name5=Dll Libraries
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Directory5=C:\
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Extension5=dll
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Name6=PDF
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Directory6=C:\
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Extension6=pdf
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Name7=HTML
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Directory7=C:\
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Extension7=
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[sdf.c.structure_con]
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[sdf.ea.tb_usbrx-rtl]
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0=src\testbench\usbrx_vhdl_usbrx_vhdl_vho.sdf| /tb_usbrx/uut, Average, No
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[Groups]
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mt_toolbox=1
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mt_filter=1
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usbrx=1
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usbrx\filter=1
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usbrx\datapath=1
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usbrx\toplevel=1
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testbench=1
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[Files]
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mt_toolbox/mt_toolbox.vhd=-1
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mt_toolbox/mt_clktools.vhd=-1
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mt_filter/mt_filter.vhd=-1
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mt_filter/mt_fil_storage_slow.vhd=-1
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mt_filter/mt_fil_mac_slow.vhd=-1
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mt_filter/mt_fir_symmetric_slow.vhd=-1
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usbrx/usbrx.vhd=-1
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usbrx\filter/usbrx_halfband.vhd=-1
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usbrx\datapath/usbrx_ad7357.vhd=-1
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usbrx\datapath/usbrx_offset.vhd=-1
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usbrx\datapath/usbrx_decimate.vhd=-1
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usbrx\datapath/usbrx_ssc.vhd=-1
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usbrx\toplevel/usbrx_clkgen.vhd=-1
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usbrx\toplevel/usbrx_spi.vhd=-1
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usbrx\toplevel/usbrx_regbank.vhd=-1
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usbrx\toplevel/usbrx_pwm.vhd=-1
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usbrx\toplevel/usbrx_toplevel.vhd=-1
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testbench/tb_filter.vhd=-1
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testbench/tb_usbrx.vhd=-1
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[Files.Data]
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.\src\mt_toolbox\mt_toolbox.vhd=VHDL Source Code
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.\src\mt_toolbox\mt_clktools.vhd=VHDL Source Code
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.\src\mt_filter\mt_filter.vhd=VHDL Source Code
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.\src\mt_filter\mt_fil_storage_slow.vhd=VHDL Source Code
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.\src\mt_filter\mt_fil_mac_slow.vhd=VHDL Source Code
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.\src\mt_filter\mt_fir_symmetric_slow.vhd=VHDL Source Code
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.\src\usbrx\usbrx.vhd=VHDL Source Code
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.\src\usbrx\filter\usbrx_halfband.vhd=VHDL Source Code
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.\src\usbrx\datapath\usbrx_ad7357.vhd=VHDL Source Code
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.\src\usbrx\datapath\usbrx_offset.vhd=VHDL Source Code
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.\src\usbrx\datapath\usbrx_decimate.vhd=VHDL Source Code
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.\src\usbrx\datapath\usbrx_ssc.vhd=VHDL Source Code
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.\src\usbrx\toplevel\usbrx_clkgen.vhd=VHDL Source Code
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.\src\usbrx\toplevel\usbrx_spi.vhd=VHDL Source Code
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.\src\usbrx\toplevel\usbrx_regbank.vhd=VHDL Source Code
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.\src\usbrx\toplevel\usbrx_pwm.vhd=VHDL Source Code
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.\src\usbrx\toplevel\usbrx_toplevel.vhd=VHDL Source Code
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.\src\testbench\tb_filter.vhd=VHDL Source Code
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.\src\testbench\tb_usbrx.vhd=VHDL Test Bench
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