101 lines
3.1 KiB
VHDL
101 lines
3.1 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_pwm.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : PWM Generator
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.usbrx.all;
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entity usbrx_pwm is
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port(
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- config
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config : in usbrx_pwm_config_t;
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-- PWM output
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pwm0 : out std_logic;
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pwm1 : out std_logic
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);
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end usbrx_pwm;
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architecture rtl of usbrx_pwm is
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-- status
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signal counter0 : unsigned(15 downto 0);
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signal counter1 : unsigned(15 downto 0);
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signal out0 : std_logic;
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signal out1 : std_logic;
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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-- update counter #0
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counter0 <= counter0 - 1;
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if counter0 = 0 then
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counter0 <= config.freq0;
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end if;
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-- update counter #1
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counter1 <= counter1 - 1;
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if counter1 = 0 then
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counter1 <= config.freq1;
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end if;
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-- update output #0
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if counter0 < config.duty0
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then out0 <= '1';
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else out0 <= '0';
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end if;
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-- update output #1
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if counter1 < config.duty1
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then out1 <= '1';
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else out1 <= '0';
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end if;
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-- output register
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pwm0 <= out0;
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pwm1 <= out1;
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-- handle reset
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if reset='1' then
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counter0 <= (others=>'0');
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counter1 <= (others=>'0');
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out0 <= '0';
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out1 <= '0';
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pwm0 <= '0';
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pwm1 <= '0';
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end if;
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end if;
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end process;
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end rtl;
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