506 lines
13 KiB
VHDL
506 lines
13 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_halfband.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : Multichannel Halfband Decimation Filter
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- halfband decimation filter - input cache/control ---------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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entity usbrx_halfband_ictrl is
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generic (
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N : natural := 3
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);
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port (
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- input
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in_clk : in std_logic_vector(N-1 downto 0);
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in_i : in fir_databus18(N-1 downto 0);
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in_q : in fir_databus18(N-1 downto 0);
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-- output
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out_ready : in std_logic;
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out_clk : out std_logic;
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out_chan : out unsigned(log2(N)-1 downto 0);
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out_i0 : out fir_dataword18;
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out_i1 : out fir_dataword18;
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out_q0 : out fir_dataword18;
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out_q1 : out fir_dataword18
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);
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end usbrx_halfband_ictrl;
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architecture rtl of usbrx_halfband_ictrl is
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-- control
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signal phase : std_logic_vector(N-1 downto 0);
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signal tmp_i : fir_databus18(N-1 downto 0);
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signal tmp_q : fir_databus18(N-1 downto 0);
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signal oclk : std_logic;
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-- output
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signal pending : std_logic_vector(N-1 downto 0);
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signal cache_i0 : fir_databus18(N-1 downto 0);
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signal cache_i1 : fir_databus18(N-1 downto 0);
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signal cache_q0 : fir_databus18(N-1 downto 0);
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signal cache_q1 : fir_databus18(N-1 downto 0);
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begin
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-- control logic
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process(clk)
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variable found : std_logic;
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begin
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if rising_edge(clk) then
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-- set default values
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oclk <= '0';
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-- check if we are allowed to output the next entry
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if out_ready='1' and oclk='0' then
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-- search for pending cache-entry
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found := '0';
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for i in 0 to N-1 loop
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if found='0' and pending(i)='1' then
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--> output entry
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oclk <= '1';
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out_chan <= to_unsigned(i,out_chan'length);
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out_i0 <= cache_i0(i);
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out_i1 <= cache_i1(i);
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out_q0 <= cache_q0(i);
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out_q1 <= cache_q1(i);
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-- update status
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pending(i) <= '0';
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found := '1';
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end if;
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end loop;
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end if;
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-- handle incoming samples
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for i in in_clk'range loop
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if in_clk(i)='1' then
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-- write sample into cache
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if phase(i)='0' then
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tmp_i(i) <= in_i(i);
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tmp_q(i) <= in_q(i);
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else
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pending(i) <= '1';
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cache_i0(i) <= tmp_i(i);
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cache_q0(i) <= tmp_q(i);
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cache_i1(i) <= in_i(i);
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cache_q1(i) <= in_q(i);
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end if;
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phase(i) <= not phase(i);
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-- debug check
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assert phase(i)='0' or pending(i)='0'
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report "usbrx_halfband_ictrl: input too fast"
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severity error;
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end if;
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end loop;
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-- handle reset
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if reset='1' then
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phase <= (others=>'0');
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tmp_i <= (others=>(others=>'0'));
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tmp_q <= (others=>(others=>'0'));
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pending <= (others=>'0');
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cache_i0 <= (others=>(others=>'0'));
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cache_i1 <= (others=>(others=>'0'));
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cache_q0 <= (others=>(others=>'0'));
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cache_q1 <= (others=>(others=>'0'));
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oclk <= '0';
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out_chan <= (others=>'0');
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out_i0 <= (others=>'0');
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out_i1 <= (others=>'0');
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out_q0 <= (others=>'0');
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out_q1 <= (others=>'0');
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end if;
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end if;
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end process;
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-- connect output-clock
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out_clk <= oclk;
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end rtl;
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-------------------------------------------------------------------------------
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-- halfband decimation filter - output control --------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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entity usbrx_halfband_octrl is
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generic (
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N : natural := 3
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);
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port (
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- input
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in_clk : in std_logic;
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in_chan : in unsigned(log2(2*N)-1 downto 0);
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in_data : in fir_dataword18;
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-- output
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out_clk : out std_logic_vector(N-1 downto 0);
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out_i : out fir_databus18(N-1 downto 0);
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out_q : out fir_databus18(N-1 downto 0)
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);
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end usbrx_halfband_octrl;
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architecture rtl of usbrx_halfband_octrl is
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-- cache
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signal tmp_i : fir_databus18(N-1 downto 0);
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begin
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-- control logic
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process(clk)
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variable sel : natural range 0 to N-1;
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begin
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if rising_edge(clk) then
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-- set default values
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out_clk <= (others=>'0');
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-- handle input
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if in_clk='1' then
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sel := to_integer(in_chan)/2;
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for i in out_clk'range loop
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if sel=i then
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if in_chan(0)='0' then
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-- cache result
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tmp_i(i) <= in_data;
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else
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-- output result
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out_clk(i) <= '1';
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out_i(i) <= tmp_i(i);
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out_q(i) <= in_data;
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end if;
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end if;
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end loop;
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end if;
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-- handle reset
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if reset='1' then
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tmp_i <= (others=>(others=>'0'));
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out_clk <= (others=>'0');
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out_i <= (others=>(others=>'0'));
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out_q <= (others=>(others=>'0'));
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end if;
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end if;
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end process;
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end rtl;
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-------------------------------------------------------------------------------
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-- halfband decimation filter -------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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entity usbrx_halfband is
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generic (
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N : natural := 3
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);
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port (
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- input
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in_clk : in std_logic_vector(N-1 downto 0);
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in_i : in fir_databus18(N-1 downto 0);
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in_q : in fir_databus18(N-1 downto 0);
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-- output
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out_clk : out std_logic_vector(N-1 downto 0);
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out_i : out fir_databus18(N-1 downto 0);
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out_q : out fir_databus18(N-1 downto 0)
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);
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end usbrx_halfband;
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architecture rtl of usbrx_halfband is
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-- internal types
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type state_t is (S_IDLE, S_FILTER_I, S_FILTER_Q, S_COOLDOWN);
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-- status
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signal state : state_t;
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-- input control
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signal ic_ready : std_logic;
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signal ic_clk : std_logic;
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signal ic_chan : unsigned(log2(N)-1 downto 0);
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signal ic_i0 : fir_dataword18;
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signal ic_i1 : fir_dataword18;
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signal ic_q0 : fir_dataword18;
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signal ic_q1 : fir_dataword18;
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-- next output
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signal on_clk : std_logic;
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signal on_chan : unsigned(log2(2*N)-1 downto 0);
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signal on_dat1 : fir_dataword18;
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signal on_dat2 : fir_dataword18;
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-- output control
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signal oc_iclk : std_logic;
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signal oc_ichan : unsigned(log2(2*N)-1 downto 0);
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signal oc_idata : fir_dataword18;
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-- FIR input
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signal fir_iclk : std_logic;
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signal fir_iack : std_logic;
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signal fir_idata : fir_dataword18;
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signal fir_ichan : unsigned(log2(2*N)-1 downto 0);
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-- FIR output
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signal fir_oclk : std_logic;
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signal fir_ochan : unsigned(log2(2*N)-1 downto 0);
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signal fir_odata : fir_dataword18;
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-- center samples
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signal cent_i : fir_databus18(N-1 downto 0);
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signal cent_q : fir_databus18(N-1 downto 0);
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-- coefficients for 2x-FIR-interpolator
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-- (halfband, order 48, wpass 0.40)
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constant coeffs : fir_coefficients(0 to 11) := (
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-52, 151, -354, 715,
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-1307, 2227, -3614, 5691,
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-8907, 14403, -26386, 82957
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);
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begin
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-- control logic
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process(clk)
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variable sel : natural range 0 to N-1;
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begin
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if rising_edge(clk) then
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-- set default values
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fir_iclk <= '0';
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oc_iclk <= '0';
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on_clk <= '0';
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-- filter control
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case state is
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when S_IDLE =>
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-- wait for new sample-pair
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if ic_clk='1' then
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-- start filter (I)
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fir_iclk <= '1';
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fir_idata <= ic_i1;
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fir_ichan <= resize(ic_chan & "0", fir_ichan'length);
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-- update status
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state <= S_FILTER_I;
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end if;
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when S_FILTER_I =>
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-- wait until filtering is done
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if fir_iack='1' then
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-- start filter (Q)
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fir_iclk <= '1';
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fir_idata <= ic_q1;
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fir_ichan <= resize(ic_chan & "1", fir_ichan'length);
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-- update status
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state <= S_FILTER_Q;
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end if;
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when S_FILTER_Q =>
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-- wait until filtering is done
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if fir_iack='1' then
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-- update status
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state <= S_COOLDOWN;
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end if;
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when S_COOLDOWN =>
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-- TODO: get rid of state
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if fir_oclk='1' then
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state <= S_IDLE;
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end if;
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end case;
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-- fetch FIR result and corresonding center-sample
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if fir_oclk='1' then
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on_clk <= '1';
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on_chan <= fir_ochan;
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on_dat1 <= fir_odata;
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sel := to_integer(fir_ochan)/2;
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if fir_ochan(0)='0'
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then on_dat2 <= cent_i(sel);
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else on_dat2 <= cent_q(sel);
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end if;
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end if;
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-- create final result
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if on_clk='1' then
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oc_iclk <= '1';
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oc_ichan <= on_chan;
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oc_idata <= resize((resize(on_dat1,19) + resize(on_dat2,19)) / 2,18);
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end if;
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-- handle reset
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if reset='1' then
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state <= S_IDLE;
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fir_iclk <= '0';
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fir_idata <= (others=>'0');
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fir_ichan <= (others=>'0');
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oc_iclk <= '0';
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oc_ichan <= (others=>'0');
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oc_idata <= (others=>'0');
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on_clk <= '0';
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on_chan <= (others=>'0');
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on_dat1 <= (others=>'0');
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on_dat2 <= (others=>'0');
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end if;
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end if;
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end process;
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-- create ready-flag
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ic_ready <= '1' when state=S_IDLE else '0';
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-- shift register for center-sample
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sreg: for i in 0 to N-1 generate
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subtype entry_t is signed(35 downto 0);
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type sreg_t is array(natural range<>) of entry_t;
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signal sreg : sreg_t(11 downto 0) := (others=>(others=>'0'));
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begin
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-- infer shift-register
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process(clk)
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variable temp : entry_t;
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begin
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if rising_edge(clk) then
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if ic_clk='1' and to_integer(ic_chan)=i then
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temp := ic_q0 & ic_i0;
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sreg <= sreg(sreg'left-1 downto 0) & temp;
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end if;
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end if;
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end process;
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-- output center-sample
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cent_i(i) <= sreg(sreg'left)(17 downto 0);
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cent_q(i) <= sreg(sreg'left)(35 downto 18);
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end generate;
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-- input control
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ic: entity usbrx_halfband_ictrl
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generic map (
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N => N
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)
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- input
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in_clk => in_clk,
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in_i => in_i,
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in_q => in_q,
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-- output
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out_ready => ic_ready,
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out_clk => ic_clk,
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out_chan => ic_chan,
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out_i0 => ic_i0,
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out_i1 => ic_i1,
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out_q0 => ic_q0,
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out_q1 => ic_q1
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);
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-- FIR filter core
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fir: entity mt_fir_symmetric_slow
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generic map (
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CHANNELS => 2*N,
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TAPS => 12,
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COEFFS => coeffs,
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RAMSTYLE => "block_ram",
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ROMSTYLE => "logic"
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)
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- input port
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in_clk => fir_iclk,
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in_ack => fir_iack,
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in_data => fir_idata,
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in_chan => fir_ichan,
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-- output port
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out_clk => fir_oclk,
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out_chan => fir_ochan,
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out_data => fir_odata
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);
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-- output control
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oc: entity usbrx_halfband_octrl
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generic map (
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N => N
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)
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- input
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in_clk => oc_iclk,
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in_chan => oc_ichan,
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in_data => oc_idata,
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-- output
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out_clk => out_clk,
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out_i => out_i,
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out_q => out_q
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);
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end rtl;
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