106 lines
3.4 KiB
VHDL
106 lines
3.4 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_halfband.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : Programmable sample value offset
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.usbrx.all;
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entity usbrx_offset is
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port (
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- config
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config : in usbrx_off_config_t;
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-- input
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in_clk : in std_logic;
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in_i : in unsigned(13 downto 0);
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in_q : in unsigned(13 downto 0);
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-- output
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out_clk : out std_logic;
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out_i : out signed(15 downto 0);
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out_q : out signed(15 downto 0)
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);
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end usbrx_offset;
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architecture rtl of usbrx_offset is
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-- clip & saturate sample
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function doClipValue(x : signed) return signed is
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begin
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if x >= 32768 then
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-- overflow
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return to_signed(+32767,16);
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elsif x < -32768 then
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-- underflow
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return to_signed(-32768,16);
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else
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-- in range
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return x(15 downto 0);
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end if;
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end doClipValue;
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begin
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-- control logic
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process(clk)
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variable s16i, s16q : signed(15 downto 0);
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variable s17i, s17q : signed(16 downto 0);
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begin
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if rising_edge(clk) then
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-- passthough clock
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out_clk <= in_clk;
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-- handle data
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if in_clk='1' then
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-- convert input into 16bit signed
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s16i := signed(in_i xor "10000000000000") & "00";
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s16q := signed(in_q xor "10000000000000") & "00";
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-- add offset
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s17i := resize(s16i,17) + resize(config.ioff,17);
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s17q := resize(s16q,17) + resize(config.qoff,17);
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-- clip output
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out_i <= doClipValue(s17i);
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out_q <= doClipValue(s17q);
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end if;
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-- handle reset
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if reset='1' then
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out_clk <= '0';
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out_i <= (others=>'0');
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out_q <= (others=>'0');
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end if;
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end if;
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end process;
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end rtl;
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