219 lines
6.3 KiB
VHDL
219 lines
6.3 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_decimate.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : Variable decimation filter
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-- (possible factors: 1,2,4,8,16,32,64)
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- decimation filter ----------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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use work.usbrx.all;
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entity usbrx_decimate is
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port (
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- config
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config : in usbrx_fil_config_t;
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-- input
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in_clk : in std_logic;
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in_i : in signed(15 downto 0);
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in_q : in signed(15 downto 0);
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-- output
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out_clk : out std_logic;
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out_i : out signed(15 downto 0);
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out_q : out signed(15 downto 0)
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);
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end usbrx_decimate;
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architecture rtl of usbrx_decimate is
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-- config
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signal active : std_logic_vector(5 downto 0);
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-- adapted input
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signal in_si : fir_dataword18;
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signal in_sq : fir_dataword18;
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-- filter input
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signal fil_in_clk : std_logic_vector(5 downto 0);
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signal fil_in_i : fir_databus18(5 downto 0);
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signal fil_in_q : fir_databus18(5 downto 0);
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-- filter output
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signal fil_out_clk : std_logic_vector(5 downto 0);
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signal fil_out_i : fir_databus18(5 downto 0);
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signal fil_out_q : fir_databus18(5 downto 0);
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-- unclipped output
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signal nxt_clk : std_logic;
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signal nxt_i : fir_dataword18;
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signal nxt_q : fir_dataword18;
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begin
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-- convert input into 18bit signed
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in_si <= signed(in_i) & "00";
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in_sq <= signed(in_q) & "00";
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-- control logic
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process(clk)
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variable tmp_i,tmp_q : fir_dataword18;
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begin
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if rising_edge(clk) then
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-- get active stages
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case to_integer(config.decim) is
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when 0 => active <= "000000";
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when 1 => active <= "000001";
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when 2 => active <= "000011";
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when 3 => active <= "000111";
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when 4 => active <= "001111";
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when 5 => active <= "011111";
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when others => active <= "111111";
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end case;
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-- select output
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case to_integer(config.decim) is
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when 0 =>
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nxt_clk <= in_clk;
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nxt_i <= in_si;
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nxt_q <= in_sq;
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when 1 =>
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nxt_clk <= fil_out_clk(0);
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nxt_i <= fil_out_i(0);
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nxt_q <= fil_out_q(0);
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when 2 =>
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nxt_clk <= fil_out_clk(1);
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nxt_i <= fil_out_i(1);
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nxt_q <= fil_out_q(1);
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when 3 =>
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nxt_clk <= fil_out_clk(2);
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nxt_i <= fil_out_i(2);
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nxt_q <= fil_out_q(2);
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when 4 =>
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nxt_clk <= fil_out_clk(3);
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nxt_i <= fil_out_i(3);
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nxt_q <= fil_out_q(3);
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when 5 =>
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nxt_clk <= fil_out_clk(4);
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nxt_i <= fil_out_i(4);
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nxt_q <= fil_out_q(4);
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when others =>
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nxt_clk <= fil_out_clk(5);
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nxt_i <= fil_out_i(5);
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nxt_q <= fil_out_q(5);
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end case;
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-- set output
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out_clk <= nxt_clk;
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if nxt_clk='1' then
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tmp_i := nxt_i + 2;
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tmp_q := nxt_q + 2;
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out_i <= tmp_i(17 downto 2);
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out_q <= tmp_q(17 downto 2);
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end if;
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-- handle reset
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if reset='1' then
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active <= (others=>'0');
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nxt_clk <= '0';
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nxt_i <= (others=>'0');
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nxt_q <= (others=>'0');
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out_clk <= '0';
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out_i <= (others=>'0');
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out_q <= (others=>'0');
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end if;
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end if;
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end process;
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process(in_clk,in_si,in_sq,fil_out_clk,fil_out_i,fil_out_q,active)
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begin
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-- feed first filter stage
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fil_in_clk(0) <= in_clk and active(0);
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fil_in_i(0) <= in_si;
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fil_in_q(0) <= in_sq;
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-- chain remaining filter stages
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for i in 1 to 5 loop
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fil_in_clk(i) <= fil_out_clk(i-1) and active(i-1);
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fil_in_i(i) <= fil_out_i(i-1);
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fil_in_q(i) <= fil_out_q(i-1);
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end loop;
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end process;
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-- filter instance #1 (stage 0)
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hbf1: entity usbrx_halfband
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generic map (
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N => 1
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)
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- input
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in_clk => fil_in_clk(0 downto 0),
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in_i => fil_in_i(0 downto 0),
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in_q => fil_in_q(0 downto 0),
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-- output
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out_clk => fil_out_clk(0 downto 0),
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out_i => fil_out_i(0 downto 0),
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out_q => fil_out_q(0 downto 0)
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);
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-- filter instance #2 (stage 1-5)
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hbf2: entity usbrx_halfband
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generic map (
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N => 5
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)
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- input
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in_clk => fil_in_clk(5 downto 1),
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in_i => fil_in_i(5 downto 1),
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in_q => fil_in_q(5 downto 1),
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-- output
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out_clk => fil_out_clk(5 downto 1),
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out_i => fil_out_i(5 downto 1),
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out_q => fil_out_q(5 downto 1)
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);
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end rtl;
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