357 lines
8.8 KiB
VHDL
357 lines
8.8 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_toplevel.vhd
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-- Project : OsmoSDR FPGA Firmware Testbench
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-- Purpose : Toplevel Stimulus
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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entity tb_usbrx is
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end tb_usbrx;
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architecture rtl of tb_usbrx is
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-- common
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signal clk_in_pclk : std_logic := '1';
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-- special control
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signal dings : std_logic;
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signal dingsrst : std_logic;
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-- ADC interface
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signal adc_cs : std_logic;
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signal adc_sck : std_logic;
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signal adc_sd1 : std_logic;
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signal adc_sd2 : std_logic;
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-- control SPI
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signal ctl_int : std_logic;
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signal ctl_cs : std_logic;
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signal ctl_sck : std_logic;
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signal ctl_mosi : std_logic;
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signal ctl_miso : std_logic;
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-- data SPIs
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signal rx_clk : std_logic;
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signal rx_syn : std_logic;
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signal rx_dat : std_logic;
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-- data SPIs
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signal tx_clk : std_logic := '1';
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signal tx_syn : std_logic;
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signal tx_dat : std_logic;
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-- gain PWMs
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signal gain0 : std_logic;
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signal gain1 : std_logic;
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-- GPS
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signal gps_1pps : std_logic;
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signal gps_10k : std_logic;
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-- gpios
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signal gpio : std_logic_vector(9 downto 0);
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-- virtual GNDs/VCCs
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signal vgnd : std_logic_vector(11 downto 0);
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signal vcc33 : std_logic_vector(11 downto 0);
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signal vcc12 : std_logic_vector(4 downto 0);
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begin
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-- generate clocks
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clk_in_pclk <= not clk_in_pclk after 500 ns / 30.0;
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tx_clk <= '0'; --not tx_clk after 500 ns / 24.0;
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-- special control
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dings <= '0';
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dingsrst <= '1'; --, '0' after 100 us, '1' after 200 us;
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-- data SPIs
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tx_syn <= '0';
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tx_dat <= '0';
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-- GPS
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gps_1pps <= '0';
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gps_10k <= '0';
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-- gpios
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gpio <= (others=>'H');
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-- dummy ADC model
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process
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-- constant word1 : unsigned(15 downto 0) := "0010000000000001";
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-- constant word2 : unsigned(15 downto 0) := "0001111111111110";
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-- constant word1 : unsigned(15 downto 0) := "0001111111111111";
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-- constant word2 : unsigned(15 downto 0) := "0001111111111111";
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variable word1 : unsigned(15 downto 0) := "0011010111001101";
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variable word2 : unsigned(15 downto 0) := "0001001111000101";
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variable sreg1 : unsigned(15 downto 0);
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variable sreg2 : unsigned(15 downto 0);
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variable cnt : natural;
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begin
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adc_sd1 <= 'Z';
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adc_sd2 <= 'Z';
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cnt := 0;
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loop
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wait until falling_edge(adc_cs);
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word1 := to_unsigned(8192 + cnt, 16);
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word2 := to_unsigned(8192 - cnt, 16);
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cnt := (cnt + 1) mod 8192;
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sreg1 := word1;
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sreg2 := word2;
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adc_sd1 <= transport 'X', sreg1(15) after 5ns;
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adc_sd2 <= transport 'X', sreg2(15) after 5ns;
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sreg1 := shift_left(sreg1,1);
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sreg2 := shift_left(sreg2,1);
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il: loop
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wait until rising_edge(adc_cs) or falling_edge(adc_sck);
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exit when rising_edge(adc_cs);
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adc_sd1 <= transport 'X', sreg1(15) after 11.0ns;
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adc_sd2 <= transport 'X', sreg2(15) after 11.0ns;
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sreg1 := shift_left(sreg1,1);
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sreg2 := shift_left(sreg2,1);
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end loop;
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adc_sd1 <= transport 'X', 'Z' after 9.5ns;
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adc_sd2 <= transport 'X', 'Z' after 9.5ns;
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end loop;
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end process;
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-- SPI interface
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process
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-- write cycle
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procedure spi_write(addr: in integer; data: in slv32_t) is
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variable sreg : std_logic_vector(39 downto 0);
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begin
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-- assemble message
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sreg(39) := '0';
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sreg(38 downto 32) := std_logic_vector(to_unsigned(addr,7));
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sreg(31 downto 0) := data;
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-- assert CS
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ctl_sck <= '1';
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ctl_mosi <= '1';
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ctl_cs <= '0';
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wait for 250ns;
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-- clock out data
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for i in 39 downto 0 loop
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ctl_sck <= '0';
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ctl_mosi <= sreg(i);
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wait for 250ns;
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ctl_sck <= '1';
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wait for 250ns;
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end loop;
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-- deassert CS
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wait for 250ns;
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ctl_cs <= '1';
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wait for 250ns;
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end procedure spi_write;
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-- write cycle
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procedure spi_writem(addr,count: in integer; data: in slv32_array_t) is
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variable sreg : std_logic_vector(31 downto 0);
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begin
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-- assert CS
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ctl_sck <= '1';
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ctl_mosi <= '1';
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ctl_cs <= '0';
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wait for 250ns;
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-- write command
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sreg(7) := '0';
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sreg(6 downto 0) := std_logic_vector(to_unsigned(addr,7));
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for i in 7 downto 0 loop
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ctl_sck <= '0';
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ctl_mosi <= sreg(i);
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wait for 250ns;
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ctl_sck <= '1';
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wait for 250ns;
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end loop;
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--write data
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for j in 0 to count-1 loop
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sreg := data(j);
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for i in 31 downto 0 loop
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ctl_sck <= '0';
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ctl_mosi <= sreg(i);
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wait for 250ns;
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ctl_sck <= '1';
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wait for 250ns;
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end loop;
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end loop;
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-- deassert CS
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wait for 250ns;
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ctl_cs <= '1';
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wait for 250ns;
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end procedure spi_writem;
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-- read cycle
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procedure spi_read(addr,count: in integer; data: out slv32_array_t) is
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variable sreg : std_logic_vector(7 downto 0);
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begin
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-- assemble message
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sreg(7) := '1';
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sreg(6 downto 0) := std_logic_vector(to_unsigned(addr,7));
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-- assert CS
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ctl_sck <= '1';
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ctl_mosi <= '1';
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ctl_cs <= '0';
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wait for 250ns;
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-- clock out command
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for i in 7 downto 0 loop
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ctl_sck <= '0';
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ctl_mosi <= sreg(i);
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wait for 250ns;
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ctl_sck <= '1';
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wait for 250ns;
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end loop;
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wait for 50us;
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-- read data
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for j in 0 to count-1 loop
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for i in 31 downto 0 loop
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ctl_sck <= '0';
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wait for 250ns;
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data(j)(i) := ctl_miso;
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ctl_sck <= '1';
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wait for 250ns;
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if i=24 or i=16 or i=8 then
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wait for 50us;
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end if;
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end loop;
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end loop;
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-- deassert CS
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wait for 250ns;
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ctl_cs <= '1';
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wait for 250ns;
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end procedure spi_read;
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variable temp : slv32_array_t(0 to 5);
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begin
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ctl_cs <= '1';
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ctl_sck <= '1';
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ctl_mosi <= '1';
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wait for 30us;
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-- spi_write(4,x"00000001");
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-- spi_read(0,1,temp);
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-- spi_read(0,1,temp);
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-- wait;
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--
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-- temp(0) := x"00000000";
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-- temp(1) := x"12345678";
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-- temp(2) := x"9ABCDEF0";
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-- temp(3) := x"11233435";
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-- temp(4) := x"23652662";
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-- temp(5) := x"98735773";
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-- spi_writem(0,6,temp);
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--
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-- temp := (others=>x"00000000");
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-- spi_read(0,6,temp);
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wait;
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end process;
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-- unit under test
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uut: entity usbrx_toplevel
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port map (
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-- common
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clk_in_pclk => clk_in_pclk,
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-- special control
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dings => dings,
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dingsrst => dingsrst,
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-- ADC interface
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adc_cs => adc_cs,
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adc_sck => adc_sck,
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adc_sd1 => adc_sd1,
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adc_sd2 => adc_sd2,
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-- control SPI
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ctl_int => ctl_int,
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ctl_cs => ctl_cs,
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ctl_sck => ctl_sck,
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ctl_mosi => ctl_mosi,
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ctl_miso => ctl_miso,
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-- data SPIs
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rx_clk => rx_clk,
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rx_syn => rx_syn,
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rx_dat => rx_dat,
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-- data SPIs
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tx_clk => tx_clk,
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tx_syn => tx_syn,
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tx_dat => tx_dat,
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-- gain PWMs
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gain0 => gain0,
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gain1 => gain1,
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-- GPS
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gps_1pps => gps_1pps,
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gps_10k => gps_10k,
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-- gpios
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gpio => gpio,
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-- virtual GNDs/VCCs
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vgnd => vgnd,
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vcc33 => vcc33,
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vcc12 => vcc12
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);
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end rtl;
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