132 lines
3.6 KiB
VHDL
132 lines
3.6 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_toplevel.vhd
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-- Project : OsmoSDR FPGA Firmware Testbench
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-- Purpose : Decimation Filter Stimulus
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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use work.usbrx.all;
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entity tb_filter is
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end tb_filter;
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architecture rtl of tb_filter is
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-- common
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signal clk : std_logic := '1';
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signal reset : std_logic := '1';
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-- config
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signal config : usbrx_fil_config_t;
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-- input
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signal in_clk : std_logic;
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signal in_i : signed(15 downto 0);
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signal in_q : signed(15 downto 0);
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-- output
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signal out_clk : std_logic;
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signal out_i : signed(15 downto 0);
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signal out_q : signed(15 downto 0);
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begin
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-- generate clock
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clk <= not clk after 500ns / 100.0;
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reset <= '1', '0' after 123ns;
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-- set config
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config.decim <= "110";
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-- input control
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process
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variable t : real := 0.0;
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variable f : real := 1.0;
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begin
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in_clk <= '0';
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in_i <= to_signed(0,16);
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in_q <= to_signed(0,16);
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wait until rising_edge(clk) and reset='0';
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loop
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-- wait some time
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for i in 0 to 38 loop
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wait until rising_edge(clk);
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end loop;
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-- get sample data
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in_i <= to_signed(integer(cos(t)*10000.0),16);
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in_q <= to_signed(0,16);
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-- input sample
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in_clk <= '1';
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wait until rising_edge(clk);
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in_clk <= '0';
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-- update time
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t := t + f/2000000.0*2.0*MATH_PI;
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if t >= 2.0*MATH_PI then
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t := t - 2.0*MATH_PI;
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end if;
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-- update frequency
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f := f + 1.0;
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if f>1000000.0 then
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f := 1.0;
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end if;
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end loop;
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wait;
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end process;
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-- create filter core
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uut: entity usbrx_decimate
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- config
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config => config,
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-- input
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in_clk => in_clk,
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in_i => in_i,
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in_q => in_q,
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-- output
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out_clk => out_clk,
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out_i => out_i,
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out_q => out_q
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);
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end rtl;
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