183 lines
6.5 KiB
VHDL
183 lines
6.5 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : mt_toolbox.vhd
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-- Project : maintech IP-Core toolbox
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-- Purpose : maintech toolbox package
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--
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-- Description : declaration of common types, functions and attributes
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-- used throughout the toolbox
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package mt_toolbox is
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--
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-- basic types
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--
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subtype slv8_t is std_logic_vector(7 downto 0);
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subtype slv16_t is std_logic_vector(15 downto 0);
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subtype slv32_t is std_logic_vector(31 downto 0);
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subtype byte_t is unsigned(7 downto 0);
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subtype word_t is unsigned(15 downto 0);
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subtype dword_t is unsigned(31 downto 0);
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type slv8_array_t is array (natural range<>) of slv8_t;
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type slv16_array_t is array (natural range<>) of slv16_t;
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type slv32_array_t is array (natural range<>) of slv32_t;
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type byte_array_t is array (natural range<>) of byte_t;
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type word_array_t is array (natural range<>) of word_t;
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type dword_array_t is array (natural range<>) of dword_t;
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--
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-- simple helper functions
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--
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function log2(x: natural) return positive;
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--
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-- type conversion helper
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--
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function to_slv8(x: std_logic) return std_logic_vector;
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function to_slv8(x: std_logic_vector) return std_logic_vector;
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function to_slv8(x: unsigned) return std_logic_vector;
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function to_slv8(x: signed) return std_logic_vector;
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function to_slv8(x: natural) return std_logic_vector;
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function to_slv16(x: std_logic) return std_logic_vector;
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function to_slv16(x: std_logic_vector) return std_logic_vector;
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function to_slv16(x: unsigned) return std_logic_vector;
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function to_slv16(x: signed) return std_logic_vector;
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function to_slv16(x: natural) return std_logic_vector;
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function to_slv32(x: std_logic) return std_logic_vector;
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function to_slv32(x: std_logic_vector) return std_logic_vector;
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function to_slv32(x: unsigned) return std_logic_vector;
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function to_slv32(x: signed) return std_logic_vector;
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function to_slv32(x: natural) return std_logic_vector;
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--
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-- common attributes
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--
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attribute syn_keep : boolean;
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attribute syn_ramstyle : string;
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attribute syn_romstyle : string;
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end mt_toolbox;
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package body mt_toolbox is
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--
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-- simple helper functions
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--
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-- calculate ceiling base 2 logarithm (returns always >=1)
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function log2(x: natural) return positive is
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variable x_tmp: natural;
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variable y: positive;
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begin
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x_tmp := x-1;
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y := 1;
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while x_tmp > 1 loop
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y := y+1;
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x_tmp := x_tmp/2;
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end loop;
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return y;
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end;
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-- to_slv8 (pack basic types into "std_logic_vector(7 downto 0)")
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function to_slv8(x: std_logic) return std_logic_vector is
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variable res : std_logic_vector(7 downto 0);
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begin
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res := (0=>x,others=>'0');
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return res;
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end to_slv8;
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function to_slv8(x: std_logic_vector) return std_logic_vector is
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variable res : std_logic_vector(7 downto 0);
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begin
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res := (others=>'0');
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res(x'length-1 downto 0) := x;
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return res;
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end to_slv8;
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function to_slv8(x: unsigned) return std_logic_vector is
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begin
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return to_slv8(std_logic_vector(x));
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end to_slv8;
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function to_slv8(x: signed) return std_logic_vector is
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begin
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return to_slv8(std_logic_vector(x));
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end to_slv8;
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function to_slv8(x: natural) return std_logic_vector is
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begin
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return to_slv8(to_unsigned(x,8));
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end to_slv8;
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-- to_slv16 (pack basic types into "std_logic_vector(15 downto 0)")
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function to_slv16(x: std_logic) return std_logic_vector is
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variable res : std_logic_vector(15 downto 0);
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begin
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res := (0=>x,others=>'0');
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return res;
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end to_slv16;
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function to_slv16(x: std_logic_vector) return std_logic_vector is
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variable res : std_logic_vector(15 downto 0);
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begin
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res := (others=>'0');
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res(x'length-1 downto 0) := x;
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return res;
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end to_slv16;
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function to_slv16(x: unsigned) return std_logic_vector is
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begin
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return to_slv16(std_logic_vector(x));
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end to_slv16;
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function to_slv16(x: signed) return std_logic_vector is
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begin
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return to_slv16(std_logic_vector(x));
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end to_slv16;
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function to_slv16(x: natural) return std_logic_vector is
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begin
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return to_slv16(to_unsigned(x,16));
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end to_slv16;
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-- to_slv32 (pack basic types into "std_logic_vector(31 downto 0)")
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function to_slv32(x: std_logic) return std_logic_vector is
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variable res : std_logic_vector(31 downto 0);
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begin
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res := (0=>x,others=>'0');
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return res;
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end to_slv32;
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function to_slv32(x: std_logic_vector) return std_logic_vector is
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variable res : std_logic_vector(31 downto 0);
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begin
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res := (others=>'0');
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res(x'length-1 downto 0) := x;
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return res;
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end to_slv32;
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function to_slv32(x: unsigned) return std_logic_vector is
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begin
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return to_slv32(std_logic_vector(x));
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end to_slv32;
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function to_slv32(x: signed) return std_logic_vector is
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begin
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return to_slv32(std_logic_vector(x));
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end to_slv32;
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function to_slv32(x: natural) return std_logic_vector is
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begin
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return to_slv32(to_unsigned(x,32));
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end to_slv32;
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end mt_toolbox;
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