152 lines
5.0 KiB
VHDL
152 lines
5.0 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : mt_clktools.vhd
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-- Project : maintech IP-Core toolbox
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-- Purpose : Basic tools for clock/reset-generation
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- mt_reset_gen ---------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mt_reset_gen is
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port (
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clk : in std_logic; -- some direct clock-input
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ext_rst : in std_logic; -- external reset
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pll_locked : in std_logic; -- PLLs locked?
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reset_pll : out std_logic; -- reset signal for PLLs
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reset_sys : out std_logic; -- global reset signal
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-- debug
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dbg_ext : out std_logic;
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dbg_rst : out std_logic;
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dbg_lock : out std_logic
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);
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end mt_reset_gen;
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architecture rtl of mt_reset_gen is
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-- reset generation
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signal rst_roc2pll : std_logic_vector(15 downto 0) := (others=>'1'); -- delay between rst_roc <-> rst_pll
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signal rst_pll2go : std_logic_vector( 5 downto 0) := (others=>'1'); -- delay between reset_pll <-> reset_I
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signal reset_pll_i : std_logic := '1'; -- inner version of 'reset_pll'
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signal reset_sys_i : std_logic; -- inner version of 'reset_sys'
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-- TODO
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signal lockcnt : unsigned(15 downto 0) := (others=>'0');
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signal relock : std_logic := '0';
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begin
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-- generate PLL-reset
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process(clk)
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begin
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if rising_edge(clk) then
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-- if ext_rst='0' or relock='1' then
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if relock='1' then
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rst_roc2pll <= (others=>'1');
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reset_pll_i <= '1';
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else
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rst_roc2pll <= '0' & rst_roc2pll(rst_roc2pll'high downto 1);
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reset_pll_i <= rst_roc2pll(0);
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end if;
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end if;
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end process;
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-- TODO
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process(clk)
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begin
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if rising_edge(clk) then
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-- if ext_rst='0' or pll_locked='1' or relock='1' then
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if pll_locked='1' or relock='1' then
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lockcnt <= to_unsigned(0,16);
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relock <= '0';
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else
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lockcnt <= lockcnt+1;
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if lockcnt=30000-1 then
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relock <= '1';
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end if;
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end if;
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end if;
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end process;
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-- generate system-reset
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process(clk, reset_pll_i)
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begin
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if reset_pll_i = '1' then
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reset_sys_i <= '1';
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rst_pll2go <= (others=>'1');
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elsif rising_edge(clk) then
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if pll_locked='0' then
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rst_pll2go <= (others=>'1');
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reset_sys_i <= '1';
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else
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rst_pll2go <= '0' & rst_pll2go(rst_pll2go'high downto 1);
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reset_sys_i <= rst_pll2go(0);
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end if;
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end if;
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end process;
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-- output reset-signal
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reset_sys <= reset_sys_i;
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-- output PLL-reset
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reset_pll <= reset_pll_i;
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-- debug
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dbg_ext <= ext_rst;
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dbg_rst <= reset_pll_i;
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dbg_lock <= pll_locked;
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end;
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-------------------------------------------------------------------------------
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-- mt_reset_sync --------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity mt_reset_sync is
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port (
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clk : in std_logic;
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rst_in : in std_logic;
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rst_out : out std_logic
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);
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end mt_reset_sync;
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architecture rtl of mt_reset_sync is
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signal taps : std_logic_vector(3 downto 0);
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begin
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process(clk, rst_in)
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begin
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if rst_in='1' then
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taps <= (others=>'1');
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rst_out <= '1';
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elsif rising_edge(clk) then
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taps <= "0" & taps(taps'high downto 1);
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rst_out <= taps(0);
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end if;
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end process;
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end;
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