220 lines
6.3 KiB
VHDL
220 lines
6.3 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : mt_fir_symmetric_slow.vhd
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-- Project : maintech filter toolbox
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-- Purpose : Symmetric FIR filter
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-- - multiplexed input/output for all data-channels
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-- - single MAC-cell for all calculations
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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entity mt_fir_symmetric_slow is
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generic (
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CHANNELS : natural; -- number of data channels
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TAPS : natural; -- number of filter taps (AFTER folding)
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COEFFS : fir_coefficients; -- coefficent sets
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RAMSTYLE : string; -- ram style for inferred memories
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ROMSTYLE : string -- ram style for coefficent rom
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);
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port(
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- input port
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in_clk : in std_logic;
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in_ack : out std_logic;
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in_chan : in unsigned(log2(CHANNELS)-1 downto 0);
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in_data : in fir_dataword18;
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-- output port
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out_clk : out std_logic;
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out_chan : out unsigned(log2(CHANNELS)-1 downto 0);
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out_data : out fir_dataword18
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);
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end mt_fir_symmetric_slow;
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architecture rtl of mt_fir_symmetric_slow is
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-- internal types
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subtype chan_t is unsigned(log2(CHANNELS)-1 downto 0);
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type chan_array_t is array(natural range<>) of chan_t;
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-- control signals
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signal active : std_logic;
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signal shiftcnt : unsigned(log2(TAPS)-1 downto 0);
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signal ochan : chan_array_t(3 downto 0);
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-- storage ports
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signal st_chan : chan_t;
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signal st_start : std_logic;
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signal st_stop : std_logic;
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signal st_active : std_logic;
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signal st_din : fir_dataword18;
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-- storage <-> MAC
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signal st_mac_start : std_logic;
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signal st_mac_stop : std_logic;
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signal st_mac_active : std_logic;
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signal st_mac_dout1 : fir_dataword18;
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signal st_mac_dout2 : fir_dataword18;
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signal st_mac_coeff : fir_dataword18;
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-- MAC output
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signal mac_dnew : std_logic;
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signal mac_dout : fir_dataword18;
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begin
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-- control logic
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process(clk, reset)
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begin
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if reset='1' then
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active <= '0';
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shiftcnt <= (others=>'0');
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ochan <= (others=>(others=>'0'));
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st_start <= '0';
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st_stop <= '0';
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st_active <= '0';
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in_ack <= '0';
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out_clk <= '0';
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out_data <= (others=>'0');
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out_chan <= (others=>'0');
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elsif rising_edge(clk) then
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-- set default values
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in_ack <= '0';
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out_clk <= '0';
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st_start <= '0';
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st_stop <= '0';
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st_active <= '0';
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-- get current status
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if active='0' then
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--> idle
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-- check for new request
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if in_clk='1' then
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--> input new sample and start burst from storage to MAC cell
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shiftcnt <= to_unsigned(TAPS-1, shiftcnt'length);
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st_start <= '1';
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st_active <= '1';
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active <= '1';
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end if;
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else
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--> active
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-- control storage
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if shiftcnt/=0 then
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--> continue with burst
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shiftcnt <= shiftcnt-1;
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st_active <= '1';
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if shiftcnt=1 then
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-- last cycle of burst
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st_stop <= '1';
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in_ack <= '1';
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active <= '0';
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end if;
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end if;
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end if;
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-- check if new result is ready
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if mac_dnew='1' then
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--> MAC done, update output
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out_clk <= '1';
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out_chan <= ochan(ochan'left);
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out_data <= mac_dout;
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end if;
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-- delay channel-number to compensate for MAC delay
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ochan <= ochan(ochan'left-1 downto 0) & ochan(0);
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if st_mac_start='1' then
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ochan(0) <= in_chan;
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end if;
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end if;
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end process;
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-- connect storage input
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st_chan <= in_chan;
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st_din <= in_data;
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-- data storage
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st: entity mt_fil_storage_slow
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generic map (
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COEFFS => COEFFS,
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DCHAN => CHANNELS,
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TAPS => TAPS,
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RAMSTYLE => RAMSTYLE,
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ROMSTYLE => ROMSTYLE
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)
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- config
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chan => st_chan,
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-- input
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in_load => st_start,
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in_start => st_start,
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in_stop => st_stop,
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in_active => st_active,
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in_data => st_din,
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-- output
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out_load => open,
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out_start => st_mac_start,
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out_stop => st_mac_stop,
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out_active => st_mac_active,
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out_data1 => st_mac_dout1,
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out_data2 => st_mac_dout2,
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out_coeff => st_mac_coeff
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);
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-- do create MAC cell
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mac: entity mt_fil_mac_slow
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port map (
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-- common
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clk => clk,
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reset => reset,
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-- control-path
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start => st_mac_start,
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active => st_mac_active,
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presub => '0',
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-- data input
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smp1 => st_mac_dout1,
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smp2 => st_mac_dout2,
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coeff => st_mac_coeff,
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-- data output
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dnew => mac_dnew,
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dout => mac_dout
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);
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end rtl;
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