404 lines
12 KiB
VHDL
404 lines
12 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : mt_fil_storage_slow.vhd
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-- Project : maintech filter toolbox
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-- Purpose : basic data storage for FIR-like filters
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-- - version for 'slow' filter versions
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- mt_fil_dstorage_slow ------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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entity mt_fil_dstorage_slow is
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generic (
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CHANNELS : natural;
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DEPTH : natural;
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RAMSTYLE : string
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);
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port (
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- control
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chan : in unsigned(log2(CHANNELS)-1 downto 0);
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load : in std_logic;
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start : in std_logic;
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stop : in std_logic;
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active : in std_logic;
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-- datapath
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din : in fir_dataword18;
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dout1 : out fir_dataword18;
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dout2 : out fir_dataword18
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);
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end mt_fil_dstorage_slow;
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architecture rtl of mt_fil_dstorage_slow is
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--
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-- types & rams
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--
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-- derived constants
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constant MEMSIZE : natural := CHANNELS * DEPTH;
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-- internal types
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subtype offset_t is unsigned(log2(DEPTH)-1 downto 0);
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subtype addr_t is unsigned(log2(MEMSIZE)-1 downto 0);
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subtype data_t is fir_dataword18;
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type atab_t is array(CHANNELS-1 downto 0) of addr_t;
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type pram_t is array(CHANNELS-1 downto 0) of offset_t;
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type sram_t is array(MEMSIZE-1 downto 0) of data_t;
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-- create address tables
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function get_addr_tab return atab_t is
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variable res : atab_t;
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begin
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for i in res'range loop
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res(i) := to_unsigned(i*DEPTH, addr_t'length);
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end loop;
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return res;
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end get_addr_tab;
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constant addr_tab : atab_t := get_addr_tab;
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-- ram ports
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signal sram1_we : std_logic;
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signal sram1_waddr : addr_t;
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signal sram1_wdata : data_t;
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signal sram1_re : std_logic;
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signal sram1_raddr : addr_t;
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signal sram1_rdata : data_t := (others=>'0');
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signal sram2_we : std_logic;
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signal sram2_waddr : addr_t;
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signal sram2_wdata : data_t;
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signal sram2_re : std_logic;
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signal sram2_raddr : addr_t;
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signal sram2_rdata : data_t := (others=>'0');
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-- actual rams
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signal pram : pram_t := (others=>(others=>'0'));
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signal sram1 : sram_t := (others=>(others=>'0'));
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signal sram2 : sram_t := (others=>(others=>'0'));
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-- configure rams
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attribute syn_ramstyle of pram : signal is "logic";
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attribute syn_ramstyle of sram1 : signal is RAMSTYLE;
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attribute syn_ramstyle of sram2 : signal is RAMSTYLE&",no_rw_check";
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--
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-- status
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--
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-- delayed control signals
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signal start_del : std_logic_vector(1 downto 0);
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signal load_del : std_logic_vector(2 downto 0);
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signal active_del : std_logic_vector(1 downto 0);
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signal stop_del : std_logic_vector(2 downto 0);
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-- status
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signal selchan : unsigned(log2(CHANNELS)-1 downto 0);
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signal baseaddr : addr_t;
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signal woffset : offset_t;
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signal roffset1 : offset_t;
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signal roffset2 : offset_t;
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begin
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-- validate generics
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assert DEPTH>1
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report "mt_fil_dstorage_slow: DEPTH must be larger than 1"
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severity FAILURE;
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-- control logic
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process(clk, reset)
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variable offset : offset_t;
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begin
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if reset='1' then
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start_del <= (others=>'0');
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load_del <= (others=>'0');
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active_del <= (others=>'0');
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stop_del <= (others=>'0');
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selchan <= (others=>'0');
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baseaddr <= (others=>'0');
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woffset <= (others=>'0');
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roffset1 <= (others=>'0');
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roffset2 <= (others=>'0');
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sram1_re <= '0';
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sram1_we <= '0';
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sram1_raddr <= (others=>'0');
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sram1_waddr <= (others=>'0');
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sram1_wdata <= (others=>'0');
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sram2_re <= '0';
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sram2_we <= '0';
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sram2_raddr <= (others=>'0');
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sram2_waddr <= (others=>'0');
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sram2_wdata <= (others=>'0');
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elsif rising_edge(clk) then
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-- set default values
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sram1_re <= '0';
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sram1_we <= '0';
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sram2_re <= '0';
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sram2_we <= '0';
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-- create delayed flags
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start_del <= start_del(start_del'left-1 downto 0) & start;
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load_del <= load_del(load_del'left-1 downto 0) & load;
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active_del <= active_del(active_del'left-1 downto 0) & active;
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stop_del <= stop_del(stop_del'left-1 downto 0) & stop;
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-- init status on start of burst
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if start='1' then
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-- remember channel
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selchan <= chan;
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-- get base-address for selected channels
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baseaddr <= addr_tab(to_integer(chan));
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-- init pointers
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offset := pram(to_integer(chan));
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woffset <= offset;
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roffset1 <= offset;
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if offset=(DEPTH-1)
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then roffset2 <= to_unsigned(0,roffset2'length);
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else roffset2 <= offset + 1;
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end if;
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end if;
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-- store sample into ram and increment write-pointer if 'load'-flag is set
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if load_del(0)='1' then
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-- write sample into ram
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sram1_we <= '1';
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sram1_waddr <= baseaddr + woffset;
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sram1_wdata <= din;
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-- update write-pointer
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woffset <= roffset2; -- 'roffset2' is actually "((woffset+1) mod DEPTH)" here
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end if;
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if load_del(1)='1' then
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-- write-back updated write-pointer
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pram(to_integer(selchan)) <= woffset;
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end if;
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-- carry sample from sram1 into sram2 if 'stop'-flag is set
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if load_del(1)='1' then
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sram2_waddr <= baseaddr + woffset;
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end if;
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if stop_del(2)='1' then
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sram2_we <= '1';
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sram2_wdata <= sram1_rdata;
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end if;
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-- issue read-requests when active
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if active_del(0)='1' then
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-- read samples from ram
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sram1_re <= '1';
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sram2_re <= '1';
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sram1_raddr <= baseaddr + roffset1;
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sram2_raddr <= baseaddr + roffset2;
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-- update read-pointers
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if roffset1=0
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then roffset1 <= to_unsigned(DEPTH-1,roffset1'length);
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else roffset1 <= roffset1 - 1;
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end if;
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if roffset2=(DEPTH-1)
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then roffset2 <= to_unsigned(0,roffset2'length);
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else roffset2 <= roffset2 + 1;
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end if;
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end if;
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end if;
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end process;
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-- set output
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dout1 <= sram1_rdata when load_del(2)='0' else din;
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dout2 <= sram2_rdata;
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-- infer rams
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process(clk)
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begin
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if rising_edge(clk) then
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if sram1_we='1' then
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sram1(to_integer(sram1_waddr)) <= sram1_wdata;
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end if;
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if sram1_re='1' then
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sram1_rdata <= sram1(to_integer(sram1_raddr));
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end if;
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if sram2_we='1' then
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sram2(to_integer(sram2_waddr)) <= sram2_wdata;
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end if;
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if sram2_re='1' then
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sram2_rdata <= sram2(to_integer(sram2_raddr));
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end if;
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end if;
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end process;
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end rtl;
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-------------------------------------------------------------------------------
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-- mt_fil_storage_slow --------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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entity mt_fil_storage_slow is
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generic (
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COEFFS : fir_coefficients; -- coefficients
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DCHAN : natural; -- number of data channels
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TAPS : natural; -- number of samples in each segment
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RAMSTYLE : string; -- ram style for inferred memories
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ROMSTYLE : string -- ram style for coefficent rom
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);
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port (
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- config
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chan : in unsigned(log2(DCHAN)-1 downto 0);
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-- input
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in_load : in std_logic;
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in_start : in std_logic;
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in_stop : in std_logic;
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in_active : in std_logic;
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in_data : in fir_dataword18;
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-- output
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out_load : out std_logic;
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out_start : out std_logic;
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out_stop : out std_logic;
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out_active : out std_logic;
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out_data1 : out fir_dataword18;
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out_data2 : out fir_dataword18;
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out_coeff : out fir_dataword18
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);
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end mt_fil_storage_slow;
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architecture rtl of mt_fil_storage_slow is
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-- status
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signal del_load : std_logic_vector(1 downto 0);
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signal del_start : std_logic_vector(1 downto 0);
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signal del_stop : std_logic_vector(1 downto 0);
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signal del_active : std_logic_vector(1 downto 0);
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signal cind : unsigned(log2(TAPS)-1 downto 0);
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-- coeff rom
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constant rom_size : natural := 1 * (2**log2(TAPS));
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type rom_t is array (0 to rom_size-1) of fir_dataword18;
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function generate_rom return rom_t is
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variable rom : rom_t;
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variable ssize : natural;
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begin
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ssize := 2**log2(TAPS);
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rom := (others=>(others=>'0'));
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for t in 0 to TAPS-1 loop
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rom(t) := to_signed(COEFFS(t), 18);
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end loop;
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return rom;
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end generate_rom;
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signal rom : rom_t := generate_rom;
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-- don't waste blockram
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attribute syn_romstyle of rom : signal is ROMSTYLE;
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attribute syn_ramstyle of rom : signal is ROMSTYLE;
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begin
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-- data-buffer
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dbuf: entity mt_fil_dstorage_slow
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generic map (
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CHANNELS => DCHAN,
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DEPTH => TAPS,
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RAMSTYLE => RAMSTYLE
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)
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port map (
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clk => clk,
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reset => reset,
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chan => chan,
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load => in_load,
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start => in_start,
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stop => in_stop,
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active => in_active,
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din => in_data,
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dout1 => out_data1,
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dout2 => out_data2
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);
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-- control logic
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process(clk, reset)
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begin
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if reset='1' then
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del_load <= (others=>'0');
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del_start <= (others=>'0');
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del_stop <= (others=>'0');
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del_active <= (others=>'0');
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out_load <= '0';
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out_start <= '0';
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out_stop <= '0';
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out_active <= '0';
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out_coeff <= (others=>'0');
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cind <= (others=>'0');
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elsif rising_edge(clk) then
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-- create delayed control flags
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del_load <= del_load(del_load'left-1 downto 0) & in_load;
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del_start <= del_start(del_start'left-1 downto 0) & in_start;
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del_stop <= del_stop(del_stop'left-1 downto 0) & in_stop;
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del_active <= del_active(del_active'left-1 downto 0) & in_active;
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-- output delayed control flags
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out_load <= del_load(1);
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out_start <= del_start(1);
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out_stop <= del_stop(1);
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out_active <= del_active(1);
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-- update coeff-indices
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if del_start(0)='1' then
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cind <= to_unsigned(0, cind'length);
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elsif del_active(0)='1' then
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cind <= cind + 1;
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end if;
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-- output coefficent
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out_coeff <= rom(to_integer(cind));
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end if;
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end process;
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end rtl;
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