147 lines
4.7 KiB
VHDL
147 lines
4.7 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : mt_fil_mac_slow.vhd
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-- Project : maintech filter toolbox
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-- Purpose : MAC cell for FIR-like filters
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-- - version for 'slow' filter versions
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- mt_fil_mac_slow ------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.mt_filter.all;
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entity mt_fil_mac_slow is
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port (
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- control-path
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start : in std_logic;
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active : in std_logic;
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presub : in std_logic;
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-- data input
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smp1 : in fir_dataword18;
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smp2 : in fir_dataword18;
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coeff : in fir_dataword18;
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-- data output
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dnew : out std_logic;
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dout : out fir_dataword18
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);
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end mt_fil_mac_slow;
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architecture rtl of mt_fil_mac_slow is
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-- rounding constant (16 bits will get truncated)
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constant RNDVAL : natural := (2**16/2);
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-- control signals
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signal done : std_logic;
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signal active_del : std_logic_vector(2 downto 0);
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signal start_del : std_logic_vector(2 downto 0);
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signal done_del : std_logic_vector(2 downto 0);
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-- data registers
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signal psreg : std_logic;
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signal dreg : signed(17 downto 0);
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signal b0reg : signed(17 downto 0);
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signal b1reg : signed(18 downto 0);
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signal a0reg : signed(17 downto 0);
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signal a1reg : signed(17 downto 0);
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signal mreg : signed(35 downto 0);
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signal preg : signed(35 downto 0);
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begin
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-- create done-flag after 'active' goes low or 'start' is set while still active
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done <= (start or (not active)) and active_del(0);
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-- create delayed control-signals
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process(clk)
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begin
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if rising_edge(clk) then
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active_del <= active_del(active_del'left-1 downto 0) & active;
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start_del <= start_del(start_del'left-1 downto 0) & start;
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done_del <= done_del(done_del'left-1 downto 0) & done;
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end if;
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end process;
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-- do math
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process(clk)
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begin
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if rising_edge(clk) then
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-- simple storage registers
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psreg <= presub;
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dreg <= smp1;
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b0reg <= smp2;
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a0reg <= coeff;
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a1reg <= a0reg;
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-- pre-adder
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if psreg='1'
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then b1reg <= resize(b0reg,19) - resize(dreg,19);
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else b1reg <= resize(b0reg,19) + resize(dreg,19);
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end if;
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-- multiplier
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mreg <= a1reg * b1reg(18 downto 1);
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-- post-adder / accumulator
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if active_del(2)='1' then
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if start_del(2)='1'
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then preg <= mreg + to_signed(RNDVAL,36);
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else preg <= mreg + preg;
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end if;
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end if;
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end if;
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end process;
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-- update output
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process(reset, clk)
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begin
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if reset='1' then
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dnew <= '0';
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dout <= (others=>'0');
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elsif rising_edge(clk) then
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if done_del(2)='1' then
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dnew <= '1';
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if preg(35)='0' and preg(34 downto 33)/="00" then
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dout <= to_signed(2**17-1,18);
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elsif preg(35)='1' and preg(34 downto 33)/="11" then
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dout <= to_signed(-(2**17),18);
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else
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dout <= preg(33 downto 16);
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end if;
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else
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dnew <= '0';
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end if;
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end if;
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end process;
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end rtl;
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