159 lines
4.4 KiB
VHDL
159 lines
4.4 KiB
VHDL
---------------------------------------------------------------------------------------------------
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-- Filename : usbrx_clkref.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : Reference Clock Measurement
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.usbrx.all;
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entity usbrx_clkref is
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port(
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-- system clocks
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clk_sys : in std_logic;
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rst_sys : in std_logic;
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-- reference signal
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clk_ref : in std_logic;
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rst_ref : in std_logic;
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-- 1pps signal
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gps_1pps : in std_logic;
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-- status
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status : out usbrx_ref_status_t
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);
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end usbrx_clkref;
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architecture rtl of usbrx_clkref is
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-- deglitcher
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signal dgl_hist : std_logic_vector(3 downto 0);
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signal dgl_out : std_logic;
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-- edge detection
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signal pps_last : std_logic;
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-- active counters
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signal cnt_lsb : unsigned(24 downto 0);
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-- latched counters
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signal lat_upd : std_logic;
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signal lat_lsb : unsigned(24 downto 0);
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signal lat_msb : unsigned(6 downto 0);
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-- output register
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signal out_upd : std_logic;
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signal out_lsb : unsigned(24 downto 0);
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signal out_msb : unsigned(6 downto 0);
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begin
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-- reference counter
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process(clk_ref)
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variable cnt0,cnt1 : natural range 0 to 4;
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variable re : boolean;
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begin
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if rising_edge(clk_ref) then
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-- set default values
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lat_upd <= '0';
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-- deglitch pps signal
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dgl_hist <= dgl_hist(dgl_hist'left-1 downto 0) & gps_1pps;
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cnt0 := 0;
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cnt1 := 0;
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for i in dgl_hist'range loop
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if dgl_hist(i)='0' then
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cnt0 := cnt0 + 1;
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end if;
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if dgl_hist(i)='1' then
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cnt1 := cnt1 + 1;
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end if;
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end loop;
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if cnt0 >= 3 then
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dgl_out <= '0';
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elsif cnt1 >= 3 then
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dgl_out <= '1';
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end if;
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-- detect rising edge on pps
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pps_last <= dgl_out;
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re := (dgl_out='1' and pps_last='0');
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-- update counters
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if re then
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cnt_lsb <= to_unsigned(0, cnt_lsb'length);
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lat_lsb <= cnt_lsb;
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lat_msb <= lat_msb + 1;
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lat_upd <= '1';
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else
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cnt_lsb <= cnt_lsb + 1;
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end if;
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-- handle reset
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if rst_ref='1' then
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dgl_hist <= (others=>'0');
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dgl_out <= '0';
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pps_last <= '0';
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cnt_lsb <= (others=>'0');
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lat_upd <= '0';
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lat_lsb <= (others=>'0');
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lat_msb <= (others=>'0');
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end if;
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end if;
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end process;
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-- bring update-pulse into correct clock domain
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syn: entity mt_sync_feedback
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port map (
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i_clk => clk_ref,
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i_data => lat_upd,
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o_clk => clk_sys,
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o_data => out_upd
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);
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-- output register
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process(clk_sys)
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begin
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if rising_edge(clk_sys) then
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-- update output when requested
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if out_upd='1' then
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out_lsb <= lat_lsb;
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out_msb <= lat_msb;
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end if;
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-- handle reset
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if rst_sys='1' then
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out_lsb <= (others=>'0');
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out_msb <= (others=>'0');
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end if;
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end if;
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end process;
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-- output status
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status.lsb <= out_lsb;
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status.msb <= out_msb;
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end rtl;
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