267 lines
7.0 KiB
C
267 lines
7.0 KiB
C
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/* (C) 2011-2012 by Harald Welte <laforge@gnumonks.org>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <errno.h>
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#include <pio/pio.h>
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#include <spi/spi.h>
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#include <common.h>
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#include <reg_field.h>
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#include <osdr_fpga.h>
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#define BOARD_OSDR_SPI AT91C_BASE_SPI0
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#define BOARD_OSDR_FPGA_SPI_NPCS 0
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#define OSDR_FPGA_SPCK_MAX 1000000
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#define OSDR_FPGA_NPCSCONFIG(masterClock) \
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(AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 \
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| SPI_SCBR(OSDR_FPGA_SPCK_MAX, masterClock) \
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| SPI_DLYBS(50, masterClock) \
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| SPI_DLYBCT(0, masterClock))
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static const Pin fon_pin = PIN_FON;
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static AT91S_SPI *spi = BOARD_OSDR_SPI;
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static void write_byte(uint8_t byte)
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{
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while ((spi->SPI_SR & AT91C_SPI_TDRE) == 0) {
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//printf("W SR=0x%08x ", spi->SPI_SR);
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if (spi->SPI_SR & AT91C_SPI_RDRF)
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SPI_Read(BOARD_OSDR_SPI);
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}
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spi->SPI_TDR = byte | SPI_PCS(0);
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}
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uint32_t osdr_fpga_reg_read(uint8_t reg)
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{
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uint32_t val;
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/* make sure that previous transfers have terminated */
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while ((spi->SPI_SR & AT91C_SPI_TXEMPTY) == 0);
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write_byte(0x80 | (reg & 0x7f));
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/* dummy read for command byte transfer */
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SPI_Read(BOARD_OSDR_SPI);
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write_byte(0);
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val = SPI_Read(BOARD_OSDR_SPI) << 24;
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write_byte(0);
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val |= SPI_Read(BOARD_OSDR_SPI) << 16;
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write_byte(0);
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val |= SPI_Read(BOARD_OSDR_SPI) << 8;
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write_byte(0);
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val |= SPI_Read(BOARD_OSDR_SPI);
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return val;
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}
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void osdr_fpga_reg_write(uint8_t reg, uint32_t val)
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{
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/* make sure that previous transfers have terminated */
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while ((spi->SPI_SR & AT91C_SPI_TXEMPTY) == 0);
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write_byte(reg & 0x7f);
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write_byte((val >> 24) & 0xff);
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write_byte((val >> 16) & 0xff);
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write_byte((val >> 8) & 0xff);
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write_byte((val >> 0) & 0xff);
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/* wait until transfer has finished */
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while (!SPI_IsFinished(BOARD_OSDR_SPI));
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/* make sure to flush any received characters */
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while (spi->SPI_SR & AT91C_SPI_RDRF)
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SPI_Read(BOARD_OSDR_SPI);
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}
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void osdr_fpga_power(int on)
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{
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if (on)
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PIO_Set(&fon_pin);
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else
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PIO_Clear(&fon_pin);
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}
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void osdr_fpga_set_decimation(uint8_t val)
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{
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osdr_fpga_reg_write(OSDR_FPGA_REG_DECIMATION, val);
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}
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void osdr_fpga_set_iq_swap(uint8_t val)
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{
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osdr_fpga_reg_write(OSDR_FPGA_REG_IQ_SWAP, (val & 1) ^ 1);
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}
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void osdr_fpga_set_iq_gain(uint16_t igain, uint16_t qgain)
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{
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osdr_fpga_reg_write(OSDR_FPGA_REG_IQ_GAIN, ((uint32_t)igain) | (((uint32_t)qgain) << 16));
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}
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void osdr_fpga_set_iq_ofs(int16_t iofs, int16_t qofs)
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{
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osdr_fpga_reg_write(OSDR_FPGA_REG_IQ_OFS, (((uint32_t)iofs) & 0xffff) | ((((uint32_t)qofs) << 16) & 0xffff0000));
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}
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/***********************************************************************
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* command integration
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***********************************************************************/
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static int cmd_fpga_dump(struct cmd_state *cs, enum cmd_op op,
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const char *cmd, int argc, char **argv)
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{
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uart_cmd_out(cs, "FPGA ID REG: 0x%08x\n\r", osdr_fpga_reg_read(OSDR_FPGA_REG_ID));
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uart_cmd_out(cs, "FPGA ADC: 0x%08x\n\r", osdr_fpga_reg_read(OSDR_FPGA_REG_ADC_VAL));
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uart_cmd_out(cs, "FPGA PWM1: 0x%08x\n\r", osdr_fpga_reg_read(OSDR_FPGA_REG_PWM1));
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uart_cmd_out(cs, "FPGA ADC TIMING: 0x%08x\n\r", osdr_fpga_reg_read(OSDR_FPGA_REG_ADC_TIMING));
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return 0;
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}
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static int cmd_fpga_clkdiv(struct cmd_state *cs, enum cmd_op op,
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const char *cmd, int argc, char **argv)
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{
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uint32_t tmp;
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if (argc < 1)
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return -EINVAL;
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tmp = osdr_fpga_reg_read(OSDR_FPGA_REG_ADC_TIMING);
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osdr_fpga_reg_write(OSDR_FPGA_REG_ADC_TIMING,
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(tmp & 0xFFFF0000) | atoi(argv[0]));
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return 0;
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}
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enum fpga_field {
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PWM1_DIV, PWM1_DUTY,
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PWM2_DIV, PWM2_DUTY,
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ADC_CLKDIV, ADC_DUTY,
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};
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const struct reg_field fpga_fields[] = {
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[PWM1_DIV] = { OSDR_FPGA_REG_PWM1, 0, 16 },
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[PWM1_DUTY] = { OSDR_FPGA_REG_PWM1, 16, 16 },
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[PWM2_DIV] = { OSDR_FPGA_REG_PWM2, 0, 16 },
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[PWM2_DUTY] = { OSDR_FPGA_REG_PWM2, 16, 16 },
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[ADC_CLKDIV] = { OSDR_FPGA_REG_ADC_TIMING, 0, 8 },
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[ADC_DUTY] = { OSDR_FPGA_REG_ADC_TIMING, 8, 8},
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};
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const char *field_names[] = {
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[PWM1_DIV] = "fpga.pwm1_div",
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[PWM1_DUTY] = "fpga.pwm1_duty",
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[PWM2_DIV] = "fpga.pwm2_div",
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[PWM2_DUTY] = "fpga.pwm2_duty",
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[ADC_CLKDIV] = "fpga.adc_clkdiv",
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[ADC_DUTY] = "fpga.adc_acqlen",
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};
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static int fpga_f_write(void *data, uint32_t reg, uint32_t val)
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{
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osdr_fpga_reg_write(reg, val);
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return 0;
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}
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static uint32_t fpga_f_read(void *data, uint32_t reg)
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{
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return osdr_fpga_reg_read(reg);
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}
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static const struct reg_field_ops fpga_fops = {
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.fields = fpga_fields,
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.field_names = field_names,
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.num_fields = ARRAY_SIZE(fpga_fields),
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.data = NULL,
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.write_cb = fpga_f_write,
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.read_cb = fpga_f_read,
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};
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static int cmd_fpga_field(struct cmd_state *cs, enum cmd_op op,
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const char *cmd, int argc, char **argv)
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{
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return reg_field_cmd(cs, op, cmd, argc, argv, &fpga_fops);
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}
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static int cmd_fpga_test(struct cmd_state *cs, enum cmd_op op,
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const char *cmd, int argc, char **argv)
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{
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uint32_t on;
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/* in the test mode, the FPGA will not send samples but an incrementing
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* and decrementing counter to detect lost samples. */
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switch (op) {
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case CMD_OP_SET:
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if (atoi(argv[0]) == 0)
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on = 0;
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else
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on = 1;
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osdr_fpga_reg_write(4, on);
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break;
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case CMD_OP_GET:
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printf("FPGA Test mode is %u\n\r", osdr_fpga_reg_read(4));
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break;
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}
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return 0;
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}
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static struct cmd cmds[] = {
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{ "fpga.dump", CMD_OP_EXEC, cmd_fpga_dump,
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"Dump FPGA registers" },
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{ "fpga.pwm1_div", CMD_OP_SET|CMD_OP_GET, cmd_fpga_field,
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"PWM divider, Freq = 80MHz/(div+1)" },
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{ "fpga.pwm1_duty", CMD_OP_SET|CMD_OP_GET, cmd_fpga_field,
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"PWM duty cycle" },
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{ "fpga.pwm2_div", CMD_OP_SET|CMD_OP_GET, cmd_fpga_field,
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"PWM divider, Freq = 80MHz/(div+1)" },
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{ "fpga.pwm2_duty", CMD_OP_SET|CMD_OP_GET, cmd_fpga_field,
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"PWM duty cycle" },
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{ "fpga.adc_clkdiv", CMD_OP_SET|CMD_OP_GET, cmd_fpga_field,
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"FPGA Clock Divider for ADC (80 MHz/CLKDIV)" },
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{ "fpga.adc_acqlen", CMD_OP_SET|CMD_OP_GET, cmd_fpga_field,
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"Num of SCK cycles nCS to AD7357 is held high betewen conversions" },
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{ "fpga.test_mode", CMD_OP_SET|CMD_OP_GET, cmd_fpga_test,
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"Enable/disable test mode" },
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};
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/***********************************************************************
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* global init function
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***********************************************************************/
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void osdr_fpga_init(uint32_t masterClock)
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{
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SPI_Configure(BOARD_OSDR_SPI, AT91C_ID_SPI0,
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AT91C_SPI_MSTR | AT91C_SPI_PS_FIXED);
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SPI_ConfigureNPCS(BOARD_OSDR_SPI, 0,
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OSDR_FPGA_NPCSCONFIG(masterClock));
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SPI_Enable(BOARD_OSDR_SPI);
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uart_cmds_register(cmds, ARRAY_SIZE(cmds));
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}
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