27 lines
721 B
C
27 lines
721 B
C
#ifndef _OSDR_FGPA_H
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#define _OSDR_FGPA_H
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enum osdr_fpga_reg {
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OSDR_FPGA_REG_ID = 0,
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OSDR_FPGA_REG_PWM1 = 1,
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OSDR_FPGA_REG_PWM2 = 2,
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OSDR_FPGA_REG_ADC_TIMING = 3,
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OSDR_FPGA_REG_DUMMY = 4,
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OSDR_FPGA_REG_ADC_VAL = 5,
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OSDR_FPGA_REG_DECIMATION = 6,
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OSDR_FPGA_REG_IQ_OFS = 7,
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OSDR_FPGA_REG_IQ_GAIN = 8,
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OSDR_FPGA_REG_IQ_SWAP = 9,
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};
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void osdr_fpga_power(int on);
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void osdr_fpga_init(uint32_t masterClock);
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uint32_t osdr_fpga_reg_read(uint8_t reg);
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void osdr_fpga_reg_write(uint8_t reg, uint32_t val);
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void osdr_fpga_set_decimation(uint8_t val);
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void osdr_fpga_set_iq_swap(uint8_t val);
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void osdr_fpga_set_iq_gain(uint16_t igain, uint16_t qgain);
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void osdr_fpga_set_iq_ofs(int16_t iofs, int16_t qofs);
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#endif
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