126 lines
1.7 KiB
Plaintext
126 lines
1.7 KiB
Plaintext
##########
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BUS DEFAULT NAME
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BUS
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##########
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BUS DEFAULT TYPE
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STD_LOGIC_VECTOR
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##########
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BUS GLOBAL CONNECTOR
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GlobalBus
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##########
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BUS INDEX END
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0
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##########
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BUS INDEX START
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7
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##########
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BUS TERMINAL BUFFER
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BusBuffer
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##########
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BUS TERMINAL IN
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BusInput
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##########
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BUS TERMINAL INOUT
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BusBidirectional
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##########
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BUS TERMINAL OUT
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BusOutput
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##########
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CHECK DIAGRAM
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YES
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##########
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DEFAULT BDE LANGUAGE
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VHDL
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##########
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FILE HEADER
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--
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-- file <GENERATEDFILE>
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-- generated <TIME>
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-- from <SOURCEFILE>
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-- by <GENERATORVERSION>
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--
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##########
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GLOBAL CONNECTOR
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Global
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##########
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GND DEFAULT TYPE
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STD_LOGIC
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##########
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GND DEFAULT VALUE
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'0'
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##########
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HANGING WIRE DEFAULT TYPE
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STD_LOGIC
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##########
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HANGING WIRE DEFAULT VALUE
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'Z'
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##########
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INCLUDE ACTIVE LIBRARY CLAUSE
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0
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##########
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INCREMENT NET FACTOR
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1
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##########
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INCREMENT NET START
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0
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##########
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INCREMENT NETS
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0
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##########
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LIBRARIES
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library IEEE;
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use IEEE.std_logic_1164.all;
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##########
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TERMINAL BUFFER
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Buffer
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##########
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TERMINAL IN
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Input
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##########
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TERMINAL INOUT
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Bidirectional
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##########
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TERMINAL OUT
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Output
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##########
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USE GLOBAL DEFAULTS
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1
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##########
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VCC DEFAULT TYPE
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STD_LOGIC
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##########
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VCC DEFAULT VALUE
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'1'
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##########
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VERILOG DANGLING DEFAULT VALUE
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1'bZ
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##########
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VERILOG DESIGN UNIT HEADER
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`timescale 1ps / 1ps
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##########
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VERILOG FILE HEADER
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//
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// file <GENERATEDFILE>
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// generated <TIME>
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// from <SOURCEFILE>
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// by <GENERATORVERSION>
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//
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##########
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VERILOG GND DEFAULT TYPE
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supply0
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##########
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VERILOG GND DEFAULT VALUE
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1'b0
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##########
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VERILOG VCC DEFAULT TYPE
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supply1
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##########
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VERILOG VCC DEFAULT VALUE
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1'b1
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##########
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WIRE DEFAULT NAME
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NET
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##########
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WIRE DEFAULT TYPE
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STD_LOGIC
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