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osdr_fpga: Add support for enabling test (counter) mode

This commit is contained in:
Harald Welte 2012-03-05 23:20:18 +01:00
parent df93598cc8
commit ef60309e63
1 changed files with 24 additions and 0 deletions
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24
firmware/src/osdr_fpga.c
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@ -188,6 +188,28 @@ static int cmd_fpga_field(struct cmd_state *cs, enum cmd_op op,
return reg_field_cmd(cs, op, cmd, argc, argv, &fpga_fops);
}
static int cmd_fpga_test(struct cmd_state *cs, enum cmd_op op,
const char *cmd, int argc, char **argv)
{
uint32_t on;
/* in the test mode, the FPGA will not send samples but an incrementing
* and decrementing counter to detect lost samples. */
switch (op) {
case CMD_OP_SET:
if (atoi(argv[0]) == 0)
on = 0;
else
on = 1;
osdr_fpga_reg_write(4, on);
break;
case CMD_OP_GET:
printf("FPGA Test mode is %u\n\r", osdr_fpga_reg_read(4));
break;
}
return 0;
}
static struct cmd cmds[] = {
{ "fpga.dump", CMD_OP_EXEC, cmd_fpga_dump,
"Dump FPGA registers" },
@ -203,6 +225,8 @@ static struct cmd cmds[] = {
"FPGA Clock Divider for ADC (80 MHz/CLKDIV)" },
{ "fpga.adc_acqlen", CMD_OP_SET|CMD_OP_GET, cmd_fpga_field,
"Num of SCK cycles nCS to AD7357 is held high betewen conversions" },
{ "fpga.test_mode", CMD_OP_SET|CMD_OP_GET, cmd_fpga_test,
"Enable/disable test mode" },
};