fast_source: Add FPGA_TEST_STATS #define for FPGA/SSC verification
Using fpga.test_mode=1 this code can compute statistics on the incrementing-counter-with-every-sample behaviour.
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@ -43,10 +43,25 @@ extern const USBDDriverDescriptors auddFastSourceDriverDescriptors;
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unsigned char fastsource_interfaces[3];
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static USBDDriver fast_source_driver;
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struct rctx_stats {
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uint32_t total; /* total number of samples */
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uint32_t sum_ffff; /* samples with I+Q = 0xffff */
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uint32_t sum_fffe; /* samples with I+Q = 0xfffe */
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uint32_t sum_other; /* samples with I+Q = something else */
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uint32_t delta_1; /* delta of last I to current I == 1 */
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uint32_t delta_2;
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uint32_t delta_3;
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uint32_t delta_other;
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};
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struct usb_state {
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struct llist_head queue;
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int active;
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uint8_t muted;
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#ifdef FPGA_TEST_STATS
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struct rctx_stats stats;
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#endif
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};
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static struct usb_state usb_state;
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@ -136,6 +151,8 @@ void fastsource_req_hdlr(const USBGenericRequest *request)
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/* Initialize the driver */
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void fastsource_init(void)
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{
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memset(&usb_state, 0, sizeof(usb_state));
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INIT_LLIST_HEAD(&usb_state.queue);
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USBDDriver_Initialize(&fast_source_driver, &auddFastSourceDriverDescriptors,
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@ -197,11 +214,76 @@ void fastsource_start(void)
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}
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}
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/* Use every Nth sample for computing statistics. At fpga.adc_clkdiv=2 we can
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* still do every sample (NTH=1) at 20MHz SSC clock. Above that, we have to look
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* at a sub-set only and thus increase NTH */
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#define NTH 8
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/* iterate over all samples in a given rctx and generate statistics */
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static void rctx_stats_add(struct req_ctx *rctx, struct rctx_stats *s)
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{
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uint16_t *data16;
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int inited = 0;
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//for (data16 = rctx->data; data16 < rctx->data + rctx->tot_len; data16 += 2) {
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for (data16 = rctx->data; data16 < rctx->data + rctx->tot_len; data16 += NTH*2) {
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uint32_t sum = data16[0] + data16[1];
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uint16_t diff_i, diff_q, last_i, last_q;
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s->total++;
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switch (sum) {
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case 0xFFFF:
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s->sum_ffff++;
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break;
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case 0xFFFE:
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s->sum_fffe++;
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break;
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default:
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s->sum_other++;
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break;
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}
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if (inited) {
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diff_i = (uint16_t)(last_i - data16[0]);
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diff_q = (uint16_t)(last_q - data16[0]);
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switch (diff_i) {
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case 1*NTH:
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s->delta_1++;
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break;
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case 2*NTH:
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s->delta_2++;
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break;
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case 3*NTH:
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s->delta_3++;
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break;
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default:
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s->delta_other++;
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}
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}
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inited = 1;
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last_i = data16[0];
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last_q = data16[1];
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}
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if (s->total > 0xFFFF) {
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printf("%u (f=%u/e=%u/o=%u) (1=%u/2=%u/3=%u/o=%u)\n\r",
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s->total, s->sum_ffff, s->sum_fffe, s->sum_other,
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s->delta_1, s->delta_2, s->delta_3, s->delta_other);
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memset(s, 0, sizeof(*s));
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}
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}
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/* SSC DMA informs us about completion of filling one rctx */
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void usb_submit_req_ctx(struct req_ctx *rctx)
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{
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req_ctx_set_state(rctx, RCTX_STATE_UDP_EP2_PENDING);
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#ifdef FPGA_TEST_STATS
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rctx_stats_add(rctx, &usb_state.stats);
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#endif
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//TRACE_INFO("USB rctx enqueue (%08x, %u/%u)\n\r", rctx, rctx->size, rctx->tot_len);
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req_ctx_enqueue(&usb_state.queue, rctx);
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