sdr-test-project: Add (non-functional) DMA code experiments
I've been unable to get the DMAC to pull data out of the SSC RHR so far.
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07cc0443b7
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45f0e31e20
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@ -97,6 +97,205 @@ static void power_peripherals(int on)
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}
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}
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struct reg {
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unsigned int offset;
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const char *name;
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};
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struct reg dma_regs[] = {
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{ 0, "GCFG" },
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{ 4, "EN" },
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{ 8, "SREQ" },
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{ 0xC, "CREQ" },
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{ 0x10, "LAST" },
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{ 0x20, "EBCIMR" },
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{ 0x24, "EBCISR" },
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{ 0x30, "CHSR" },
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{ 0, NULL}
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};
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struct reg dma_ch_regs[] = {
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{ 0, "SADDR" },
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{ 4, "DADDR" },
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{ 8, "DSCR" },
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{ 0xC, "CTRLA" },
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{ 0x10, "CTRLB" },
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{ 0x14, "CFG" },
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{ 0, NULL}
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};
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void reg_dump(struct reg *regs, uint32_t *base)
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{
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struct reg *r;
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for (r = regs; r->offset || r->name; r++) {
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uint32_t *addr = ((uint8_t *)base + r->offset);
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printf("%s\t%08x:\t%08x\n\r", r->name, addr, *addr);
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}
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}
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static void dma_dump_regs(void)
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{
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reg_dump(dma_regs, AT91C_BASE_HDMA);
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reg_dump(dma_ch_regs, (uint8_t *)AT91C_BASE_HDMA_CH_0 + (BOARD_SSC_DMA_CHANNEL*0x28));
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}
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static void ssc_irq_hdlr(void)
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{
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AT91S_SSC *ssc = AT91C_BASE_SSC0;
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uint8_t status = ssc->SSC_SR;
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}
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static DmaLinkList LLI_CH[MAX_SSC_LLI_SIZE];
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static int dma_complete = 0;
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static const uint32_t dummy = 0xdeadbeef;
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static void ssc_dma_single(void *dest, unsigned int len)
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{
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LED_Set(0);
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dma_complete = 0;
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memset(dest, 0, len);
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/* clear any pending interrupts */
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DMA_DisableChannel(BOARD_SSC_DMA_CHANNEL);
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DMA_GetStatus();
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DMA_SetSourceBufferMode(BOARD_SSC_DMA_CHANNEL, DMA_TRANSFER_SINGLE,
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(AT91C_HDMA_SRC_ADDRESS_MODE_FIXED >> 24));
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DMA_SetSourceBufferSize(BOARD_SSC_DMA_CHANNEL,
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#if 0
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len>>2 | AT91C_HDMA_SCSIZE_4 | AT91C_HDMA_DCSIZE_4,
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AT91C_HDMA_SRC_WIDTH_WORD >> 24,
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AT91C_HDMA_DST_WIDTH_WORD >> 28, 0);
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#else
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len>>2 | AT91C_HDMA_SCSIZE_1 | AT91C_HDMA_DCSIZE_1,
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AT91C_HDMA_SRC_WIDTH_BYTE >> 24,
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AT91C_HDMA_DST_WIDTH_BYTE >> 28, 0);
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#endif
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DMA_SetDestBufferMode(BOARD_SSC_DMA_CHANNEL, DMA_TRANSFER_SINGLE,
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(AT91C_HDMA_DST_ADDRESS_MODE_INCR >> 28));
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DMA_SetFlowControl(BOARD_SSC_DMA_CHANNEL, AT91C_HDMA_FC_PER2MEM >> 21);
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//DMA_SetFlowControl(BOARD_SSC_DMA_CHANNEL, AT91C_HDMA_FC_MEM2MEM >> 21);
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DMA_SetConfiguration(BOARD_SSC_DMA_CHANNEL, BOARD_SSC_DMA_HW_SRC_REQ_ID
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| BOARD_SSC_DMA_HW_DEST_REQ_ID
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| AT91C_HDMA_SRC_H2SEL_HW
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| AT91C_HDMA_DST_H2SEL_HW
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| AT91C_HDMA_SOD_DISABLE
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| AT91C_HDMA_FIFOCFG_LARGESTBURST);
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DMA_SetSourceAddr(BOARD_SSC_DMA_CHANNEL, &AT91C_BASE_SSC0->SSC_RHR);
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//DMA_SetSourceAddr(BOARD_SSC_DMA_CHANNEL, &dummy);
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DMA_SetDestinationAddr(BOARD_SSC_DMA_CHANNEL, (unsigned int) dest);
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dma_dump_regs();
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DMA_EnableChannel(BOARD_SSC_DMA_CHANNEL);
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printf("Initialized Single DMA (len=%u)\n\r", len);
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}
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#define DMA_CTRLA (AT91C_HDMA_SRC_WIDTH_WORD|AT91C_HDMA_DST_WIDTH_WORD|AT91C_HDMA_SCSIZE_1|AT91C_HDMA_DCSIZE_1)
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#define DMA_CTRLB (AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM | \
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AT91C_HDMA_DST_ADDRESS_MODE_INCR | \
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AT91C_HDMA_SRC_DSCR_FETCH_DISABLE | \
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AT91C_HDMA_SRC_ADDRESS_MODE_FIXED | \
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AT91C_HDMA_FC_MEM2MEM)
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//AT91C_HDMA_FC_PER2MEM)
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static void ssc_dma_llc(void *dest, unsigned int len)
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{
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LED_Set(0);
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dma_complete = 0;
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memset(dest, 0, len);
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LLI_CH[0].sourceAddress = &AT91C_BASE_SSC0->SSC_RHR;
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//LLI_CH[0].sourceAddress = &dummy;
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LLI_CH[0].destAddress = (unsigned int) dest;
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LLI_CH[0].controlA = len/4 | DMA_CTRLA;
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LLI_CH[0].controlB = DMA_CTRLB;
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LLI_CH[0].descriptor = 0;
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/* clear any pending interrupts */
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DMA_DisableChannel(BOARD_SSC_DMA_CHANNEL);
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DMA_GetStatus();
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DMA_SetDescriptorAddr(BOARD_SSC_DMA_CHANNEL, (unsigned int)&LLI_CH[0]);
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DMA_SetSourceAddr(BOARD_SSC_DMA_CHANNEL, &AT91C_BASE_SSC0->SSC_RHR);
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DMA_SetSourceBufferMode(BOARD_SSC_DMA_CHANNEL, DMA_TRANSFER_LLI,
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(AT91C_HDMA_SRC_ADDRESS_MODE_FIXED >> 24));
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DMA_SetDestBufferMode(BOARD_SSC_DMA_CHANNEL, DMA_TRANSFER_LLI,
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(AT91C_HDMA_DST_ADDRESS_MODE_INCR >> 28));
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#if 1
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DMA_SetFlowControl(BOARD_SSC_DMA_CHANNEL, AT91C_HDMA_FC_PER2MEM >> 21);
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DMA_SetConfiguration(BOARD_SSC_DMA_CHANNEL, BOARD_SSC_DMA_HW_SRC_REQ_ID \
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| BOARD_SSC_DMA_HW_DEST_REQ_ID \
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| AT91C_HDMA_SRC_H2SEL_HW \
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| AT91C_HDMA_DST_H2SEL_HW \
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| AT91C_HDMA_SOD_DISABLE \
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| AT91C_HDMA_FIFOCFG_LARGESTBURST);
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#else
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DMA_SetFlowControl(BOARD_SSC_DMA_CHANNEL, AT91C_HDMA_FC_MEM2MEM >> 21);
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DMA_SetConfiguration(BOARD_SSC_DMA_CHANNEL, AT91C_HDMA_FIFOCFG_ENOUGHSPACE);
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#endif
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dma_dump_regs();
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printf("enabling channel...\n\r");
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DMA_EnableChannel(BOARD_SSC_DMA_CHANNEL);
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#if 0
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printf("src last...\n\r");
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AT91C_BASE_HDMA->HDMA_LAST = (1 << BOARD_SSC_DMA_CHANNEL);
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printf("src xfer...\n\r");
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AT91C_BASE_HDMA->HDMA_CREQ = (1 << BOARD_SSC_DMA_CHANNEL);
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//while (AT91C_BASE_HDMA->HDMA_CREQ & (1 << BOARD_SSC_DMA_CHANNEL));
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printf("dst xfer...\n\r");
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AT91C_BASE_HDMA->HDMA_LAST = (2 << BOARD_SSC_DMA_CHANNEL);
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AT91C_BASE_HDMA->HDMA_CREQ = (2 << BOARD_SSC_DMA_CHANNEL);
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#endif
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printf("Initialized Single DMA (len=%u)\n\r", len);
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}
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#define BTC(N) (1 << N)
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#define CBTC(N) (1 << 8+N)
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#define ERR(N) (1 << 16+N)
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static void dma_irq_hdlr(void)
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{
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unsigned int status = DMA_GetStatus();
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LED_Clear(0);
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if (status & BTC(BOARD_SSC_DMA_CHANNEL)) {
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dma_complete = 1;
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LED_Clear(0);
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}
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}
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static int ssc_init(void)
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{
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SSC_DisableReceiver(AT91C_BASE_SSC0);
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SSC_Configure(AT91C_BASE_SSC0, AT91C_ID_SSC0, 0, BOARD_MCK);
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SSC_ConfigureReceiver(AT91C_BASE_SSC0, AT91C_SSC_CKS_RK | AT91C_SSC_CKO_NONE |
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AT91C_SSC_CKG_NONE | AT91C_SSC_START_RISE_RF,
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32-1 );
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#if 0
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IRQ_ConfigureIT(AT91C_ID_SSC0, 0, ssc_irq_hdlr);
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IRQ_EnableIT(AT91C_ID_SSC0);
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//SSC_EnableInterrupts(AT91C_BASE_SSC0, AT91C_SSC_RXRDY | AT91C_SSC_OVRUN);
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#endif
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SSC_EnableReceiver(AT91C_BASE_SSC0);
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/* Enable DMA controller and register interrupt handler */
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PMC_EnablePeripheral(AT91C_ID_HDMA);
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DMA_Enable();
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IRQ_ConfigureIT(AT91C_ID_HDMA, 0, dma_irq_hdlr);
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//IRQ_EnableIT(AT91C_ID_HDMA);
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DMA_EnableIt(BTC(BOARD_SSC_DMA_CHANNEL) | CBTC(BOARD_SSC_DMA_CHANNEL) |
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ERR(BOARD_SSC_DMA_CHANNEL));
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printf("initialzied SSC\n\r");
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}
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static void DisplayMenu(void)
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{
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printf("Menu:\r\n"
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@ -108,10 +307,15 @@ static void DisplayMenu(void)
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"[q] 100 MHz\r\n"
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"[w] 101 MHz\r\n"
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"[p] FPGA ID reg\r\n"
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"[a] FPGA ADC reg\r\n"
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"[s] SSC init\r\n"
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"[S] SSC single DMA xfer\r\n"
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"\r\n"
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);
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}
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static uint32_t dma_buf[1024/4];
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//------------------------------------------------------------------------------
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/// Main function
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//------------------------------------------------------------------------------
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@ -119,6 +323,7 @@ int main(void)
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{
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unsigned char key;
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unsigned char isValid;
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static int freq = 800;
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// Configure all pins
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PIO_Configure(pins, PIO_LISTSIZE(pins));
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@ -161,6 +366,13 @@ int main(void)
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printf("-- %s\n\r", BOARD_NAME);
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printf("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
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power_peripherals(1);
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si570_init(&si570, &twid, SI570_I2C_ADDR);
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set_si570_freq(30000000);
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osdr_fpga_init(SSC_MCK);
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osdr_fpga_reg_write(OSDR_FPGA_REG_ADC_TIMING, (1 << 8) | 255);
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osdr_fpga_reg_write(OSDR_FPGA_REG_PWM1, (1 << 400) | 800);
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// Enter menu loop
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while (1) {
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@ -169,6 +381,7 @@ int main(void)
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// Process user input
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key = DBGU_GetChar();
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//key = 0;
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switch (key) {
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case '0':
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@ -200,8 +413,43 @@ int main(void)
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osdr_fpga_init(SSC_MCK);
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reg = osdr_fpga_reg_read(OSDR_FPGA_REG_ID);
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printf("FPGA ID REG: 0x%08x\n\r", reg);
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osdr_fpga_reg_write(OSDR_FPGA_REG_ADC_TIMING, (1 << 8) | 255);
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}
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break;
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case 'a':
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printf("FPGA ADC: 0x%08x\n\r", osdr_fpga_reg_read(OSDR_FPGA_REG_ADC_VAL));
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printf("FPGA PWM1: 0x%08x\n\r", osdr_fpga_reg_read(OSDR_FPGA_REG_PWM1));
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printf("FPGA ADC TIMING: 0x%08x\n\r", osdr_fpga_reg_read(OSDR_FPGA_REG_ADC_TIMING));
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break;
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case '+':
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freq += 100;
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osdr_fpga_reg_write(OSDR_FPGA_REG_PWM1, ((freq/2) << 16) | freq);
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break;
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case '-':
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freq -= 100;
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osdr_fpga_reg_write(OSDR_FPGA_REG_PWM1, ((freq/2) << 16) | freq);
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break;
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case 's':
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ssc_init();
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break;
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case 'S':
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//ssc_dma_single(dma_buf, sizeof(dma_buf));
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ssc_dma_llc(dma_buf, sizeof(dma_buf));
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break;
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}
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//osdr_fpga_reg_write(OSDR_FPGA_REG_PWM1, ((freq/2) << 16) | freq);
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printf("\t\t\tcur_ssc_data = 0x%08x\n\r", AT91C_BASE_SSC0->SSC_RHR);
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{
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int i;
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for (i = 0; i < sizeof(dma_buf)/sizeof(dma_buf[0]); i++) {
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if (i == 0 || dma_buf[i] != dma_buf[i-1])
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printf("\t\t\tdma_ssc_data[%u] = 0x%08x\n\r", i, dma_buf[i]);
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}
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}
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dma_dump_regs();
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if (dma_complete) {
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printf("=======> DMA complete\n\r");
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dma_complete = 0;
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}
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}
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}
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