added accessor functions for specific FPGA registers

This commit is contained in:
Christian Daniel 2012-06-01 00:15:55 +02:00
parent 83340d0b37
commit 399d41474f
2 changed files with 28 additions and 0 deletions

View File

@ -8,11 +8,19 @@ enum osdr_fpga_reg {
OSDR_FPGA_REG_ADC_TIMING = 3,
OSDR_FPGA_REG_DUMMY = 4,
OSDR_FPGA_REG_ADC_VAL = 5,
OSDR_FPGA_REG_DECIMATION = 6,
OSDR_FPGA_REG_IQ_OFS = 7,
OSDR_FPGA_REG_IQ_GAIN = 8,
OSDR_FPGA_REG_IQ_SWAP = 9,
};
void osdr_fpga_power(int on);
void osdr_fpga_init(uint32_t masterClock);
uint32_t osdr_fpga_reg_read(uint8_t reg);
void osdr_fpga_reg_write(uint8_t reg, uint32_t val);
void osdr_fpga_set_decimation(uint8_t val);
void osdr_fpga_set_iq_swap(uint8_t val);
void osdr_fpga_set_iq_gain(uint16_t igain, uint16_t qgain);
void osdr_fpga_set_iq_ofs(int16_t iofs, int16_t qofs);
#endif

View File

@ -106,6 +106,26 @@ void osdr_fpga_power(int on)
PIO_Clear(&fon_pin);
}
void osdr_fpga_set_decimation(uint8_t val)
{
osdr_fpga_reg_write(OSDR_FPGA_REG_DECIMATION, val);
}
void osdr_fpga_set_iq_swap(uint8_t val)
{
osdr_fpga_reg_write(OSDR_FPGA_REG_IQ_SWAP, (val & 1) ^ 1);
}
void osdr_fpga_set_iq_gain(uint16_t igain, uint16_t qgain)
{
osdr_fpga_reg_write(OSDR_FPGA_REG_IQ_GAIN, ((uint32_t)igain) | (((uint32_t)qgain) << 16));
}
void osdr_fpga_set_iq_ofs(int16_t iofs, int16_t qofs)
{
osdr_fpga_reg_write(OSDR_FPGA_REG_IQ_OFS, (((uint32_t)iofs) & 0xffff) | ((((uint32_t)qofs) << 16) & 0xffff0000));
}
/***********************************************************************
* command integration