300 lines
8.2 KiB
VHDL
300 lines
8.2 KiB
VHDL
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-- Filename : usbrx_ad7357.vhd
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-- Project : OsmoSDR FPGA Firmware
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-- Purpose : AD7357 Interface
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---------------------------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library xp2;
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use xp2.all;
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use xp2.components.all;
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library work;
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use work.all;
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use work.mt_toolbox.all;
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use work.usbrx.all;
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entity usbrx_ad7357 is
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port(
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-- common
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clk : in std_logic;
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reset : in std_logic;
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-- config
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config : in usbrx_adc_config_t;
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-- ADC interface
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adc_cs : out std_logic;
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adc_sck : out std_logic;
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adc_sd1 : in std_logic;
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adc_sd2 : in std_logic;
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-- output
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out_clk : out std_logic;
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out_i : out unsigned(13 downto 0);
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out_q : out unsigned(13 downto 0)
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);
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end usbrx_ad7357;
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architecture rtl of usbrx_ad7357 is
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-- internal types
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type state_t is (S_ACQUISITION, S_CONVERT);
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-- main status
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signal state : state_t;
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signal counter : unsigned(7 downto 0);
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-- SCK generator
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signal cg_div : unsigned(7 downto 0);
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signal cg_count : unsigned(7 downto 0);
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signal cg_phase : std_logic;
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signal cg_ddr_a : std_logic;
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signal cg_ddr_b : std_logic;
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signal cg_renxt : std_logic;
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signal cg_redge : std_logic;
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-- chip select (+ delayed versions)
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signal css : std_logic_vector(3 downto 0);
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-- latch input on rising/falling edge of current cycle
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-- (+ delayed versions)
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signal latch_r : std_logic_vector(3 downto 0);
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signal latch_f : std_logic_vector(3 downto 0);
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-- input register stage #1
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signal sd1_s1r : std_logic; -- SD1 - rising edge
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signal sd1_s1f : std_logic; -- SD1 - falling edge
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signal sd2_s1r : std_logic; -- SD2 - rising edge
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signal sd2_s1f : std_logic; -- SD2 - falling edge
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-- input register stage #2
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signal sd1_s2r : std_logic; -- SD1 - rising edge
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signal sd1_s2f : std_logic; -- SD1 - falling edge
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signal sd2_s2r : std_logic; -- SD2 - rising edge
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signal sd2_s2f : std_logic; -- SD2 - falling edge
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-- input shift registers
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signal sreg1 : std_logic_vector(13 downto 0);
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signal sreg2 : std_logic_vector(13 downto 0);
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-- output latches
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signal onew : std_logic;
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signal oreg1 : std_logic_vector(13 downto 0);
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signal oreg2 : std_logic_vector(13 downto 0);
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begin
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-- SCL clock generator logic
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process(clk)
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begin
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if rising_edge(clk) then
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-- set default values
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cg_renxt <= '0';
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cg_redge <= cg_renxt;
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latch_r <= latch_r(latch_r'left-1 downto 0) & '0';
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latch_f <= latch_f(latch_f'left-1 downto 0) & '0';
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-- get config
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cg_div <= config.clkdiv;
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-- get operation mode
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if cg_div=0 or cg_div=1 then
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--> full speed, just pass through clock
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cg_ddr_a <= '0';
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cg_ddr_b <= '1';
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cg_renxt <= '1';
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latch_f(0) <= '1';
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else
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--> divided clock, update divider-logic
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if cg_count=0 then
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-- toggle clock on FE in middle of cycle
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cg_count <= cg_div - 2;
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cg_phase <= not cg_phase;
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cg_ddr_a <= cg_phase;
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cg_ddr_b <= not cg_phase;
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cg_renxt <= not cg_phase;
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latch_r(0) <= cg_phase;
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elsif cg_count=1 then
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-- toggle clock on RE after this cycle
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cg_count <= cg_div - 1;
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cg_phase <= '0'; --not cg_phase;
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cg_ddr_a <= '1'; --cg_phase;
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cg_ddr_b <= '1'; --cg_phase;
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latch_f(0) <= '1';
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else
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-- leave clock unchanged
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cg_count <= cg_count - 2;
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cg_ddr_a <= cg_phase;
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cg_ddr_b <= cg_phase;
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end if;
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-- failsafe
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if cg_count=1 and cg_div(0)='0' then
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cg_count <= cg_div - 2;
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end if;
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end if;
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-- handle reset
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if reset='1' then
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cg_div <= (others=>'1');
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cg_count <= (others=>'0');
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cg_phase <= '0';
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cg_renxt <= '0';
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cg_redge <= '0';
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cg_ddr_a <= '1';
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cg_ddr_b <= '1';
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latch_r <= (others=>'0');
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latch_f <= (others=>'0');
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end if;
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end if;
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end process;
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-- output register for SCLK
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oddr: ODDRXC
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port map (
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clk => clk,
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rst => reset,
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da => cg_ddr_a,
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db => cg_ddr_b,
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q => adc_sck
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);
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-- main control logig
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process(clk)
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begin
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if rising_edge(clk) then
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-- set default values
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css <= css(css'left-1 downto 0) & css(0);
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-- update status
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case state is
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when S_ACQUISITION =>
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-- doing ACQUISITION, wait until ready to start conversion
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if cg_redge='1' then
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-- new SCLK cycle, check if wait-counter has ellapsed
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counter <= counter - 1;
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if counter<=1 then
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--> counter ellapsed, start conversion
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state <= S_CONVERT;
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counter <= to_unsigned(15,counter'length);
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css(0) <= '0';
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end if;
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end if;
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when S_CONVERT =>
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-- doing conversion, wait until all bits are clocked out
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if cg_redge='1' then
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-- new SCLK cycle, check if bit-counter has ellapsed
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counter <= counter - 1;
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if counter=0 then
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-- all bits received, return to ACQUISITION state
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state <= S_ACQUISITION;
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counter <= config.acqlen;
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css(0) <= '1';
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end if;
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end if;
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end case;
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-- handle reset
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if reset='1' then
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state <= S_ACQUISITION; -- TODO
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counter <= (others=>'0');
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css <= (others=>'1');
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end if;
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end if;
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end process;
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-- output chip-select
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adc_cs <= css(0);
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-- input capture registers
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iddr1: IDDRXC
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port map (
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clk => clk,
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rst => '0',
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ce => '1',
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d => adc_sd1,
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qa => sd1_s1r,
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qb => sd1_s1f
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);
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iddr2: IDDRXC
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port map (
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clk => clk,
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rst => '0',
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ce => '1',
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d => adc_sd2,
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qa => sd2_s1r,
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qb => sd2_s1f
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);
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-- input data handling
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process(clk)
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begin
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if rising_edge(clk) then
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-- set default valies
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onew <= '0';
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-- register input-bits once more
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sd1_s2r <= sd1_s1r;
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sd1_s2f <= sd1_s1f;
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sd2_s2r <= sd2_s1r;
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sd2_s2f <= sd2_s1f;
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-- update shift-registers
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if latch_r(3)='1' then
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sreg1 <= sreg1(12 downto 0) & sd1_s2r;
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sreg2 <= sreg2(12 downto 0) & sd2_s2r;
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elsif latch_f(3)='1' then
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sreg1 <= sreg1(12 downto 0) & sd1_s2f;
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sreg2 <= sreg2(12 downto 0) & sd2_s2f;
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end if;
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-- latch away shift-register when requested
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if css(2)='1' and css(3)='0' then
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onew <= '1';
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oreg1 <= sreg1;
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oreg2 <= sreg2;
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end if;
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-- handle reset
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if reset='1' then
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sd1_s2r <= '0';
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sd1_s2f <= '0';
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sd2_s2r <= '0';
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sd2_s2f <= '0';
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sreg1 <= (others=>'0');
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sreg2 <= (others=>'0');
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oreg1 <= (others=>'0');
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oreg2 <= (others=>'0');
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onew <= '0';
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end if;
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end if;
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end process;
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-- set output
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out_clk <= onew;
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out_i <= unsigned(oreg1);
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out_q <= unsigned(oreg2);
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end rtl;
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