24 lines
315 B
Makefile
24 lines
315 B
Makefile
#
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# Simulation Makefile
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#
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XILINX_LIBS=\
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xilinx/glbl.v \
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xilinx/DSP48E1.v \
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xilinx/RAMB36E1.v
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OBJS=\
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sig_combine.v \
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sig_delay.v
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TESTBENCHES=\
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sig_chain_tb
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all: $(TESTBENCHES)
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%_tb: %_tb.v $(XILINX_LIBS) $(OBJS)
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iverilog -Wall -DSIM=1 -o $@ $(XILINX_LIBS) $(OBJS) $<
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clean:
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rm -f $(TESTBENCHES) *.vcd
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