From 18adc3602af4aa10ec11779b201dbae659dd83d9 Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Fri, 14 Dec 2018 19:34:37 +0100 Subject: [PATCH] gw: Import the gateware (RTL & Sim) Signed-off-by: Sylvain Munaut --- gw/Makefile | 23 + gw/sig_chain_tb.v | 80 + gw/sig_combine.v | 122 ++ gw/sig_delay.v | 121 ++ gw/xilinx/DSP48E1.v | 1550 ++++++++++++++ gw/xilinx/RAMB36E1.v | 4752 ++++++++++++++++++++++++++++++++++++++++++ gw/xilinx/glbl.v | 66 + 7 files changed, 6714 insertions(+) create mode 100644 gw/Makefile create mode 100644 gw/sig_chain_tb.v create mode 100644 gw/sig_combine.v create mode 100644 gw/sig_delay.v create mode 100644 gw/xilinx/DSP48E1.v create mode 100644 gw/xilinx/RAMB36E1.v create mode 100644 gw/xilinx/glbl.v diff --git a/gw/Makefile b/gw/Makefile new file mode 100644 index 0000000..d70a24a --- /dev/null +++ b/gw/Makefile @@ -0,0 +1,23 @@ +# +# Simulation Makefile +# + +XILINX_LIBS=\ + xilinx/glbl.v \ + xilinx/DSP48E1.v \ + xilinx/RAMB36E1.v + +OBJS=\ + sig_combine.v \ + sig_delay.v + +TESTBENCHES=\ + sig_chain_tb + +all: $(TESTBENCHES) + +%_tb: %_tb.v $(XILINX_LIBS) $(OBJS) + iverilog -Wall -DSIM=1 -o $@ $(XILINX_LIBS) $(OBJS) $< + +clean: + rm -f $(TESTBENCHES) *.vcd diff --git a/gw/sig_chain_tb.v b/gw/sig_chain_tb.v new file mode 100644 index 0000000..9ce2259 --- /dev/null +++ b/gw/sig_chain_tb.v @@ -0,0 +1,80 @@ +/* + * sig_chain_tb.v + * + * Copyright (C) 2018 sysmocom - systems for mobile communications GmbH + * + * vim: ts=4 sw=4 + */ + +`default_nettype none +`timescale 1ns/1ps + +module sig_chain_tb; + + // Signals + reg rst = 1; + reg clk = 0; + + reg data_valid; + reg [11:0] data_in; + wire [11:0] data_out; + wire [11:0] data_comb_3; + wire [14:0] cfg_delay; + + // Setup recording + initial begin + $dumpfile("sig_chain_tb.vcd"); + $dumpvars(0,sig_chain_tb); + end + + // Reset pulse + initial begin + # 21 rst = 0; + # 50000 $finish; + end + + // Clock + always #5 clk = !clk; + + // DUT + sig_delay #( + .WIDTH(12) + ) dut_A_I ( + .data_valid(data_valid), + .data_in(data_in), + .data_out(data_out), + .delay(cfg_delay), + .clk(clk), + .rst(rst) + ); + + sig_combine #( + .D_WIDTH(12), + .S_WIDTH(16), + .S_FRAC(14) + ) dut_B_I ( + .in_data_0(data_out), + .in_scale_0(16'h2000), // 0.5 + .in_chain_0(data_in), + .out_3(data_comb_3), + .clk(clk), + .rst(rst) + ); + + // Data gen + always @(posedge clk) + if (rst) + data_in <= 0; + else if (data_valid) + data_in <= data_in + 1; + + always @(posedge clk) + if (rst) + data_valid <= 1'b0; + else + data_valid <= ($random & 3) == 0; + + // Config + assign cfg_delay = 14'h00; + +endmodule // sig_chain_tb diff --git a/gw/sig_combine.v b/gw/sig_combine.v new file mode 100644 index 0000000..bd6daf5 --- /dev/null +++ b/gw/sig_combine.v @@ -0,0 +1,122 @@ +/* + * sig_combine.v + * + * Simple signal combiner using DSP48E + * + * Copyright (C) 2018 sysmocom - systems for mobile communications GmbH + * + * vim: ts=4 sw=4 + */ + +`ifdef SIM +`default_nettype none +`endif + +module sig_combine #( + parameter integer D_WIDTH = 12, + parameter integer S_WIDTH = 16, + parameter integer S_FRAC = 14 +)( + // Input + input wire [D_WIDTH-1:0] in_data_0, + input wire [S_WIDTH-1:0] in_scale_0, + input wire [D_WIDTH-1:0] in_chain_0, + + // Output + output wire [D_WIDTH-1:0] out_3, + + // Control + input wire clk, + input wire rst +); + localparam S = 25 - D_WIDTH + S_FRAC; + + // Signals + reg [17:0] in_chain_1; + + wire [47:0] pout_3; + wire [29:0] a_0; + wire [17:0] b_0; + wire [47:0] c_1; + + // Align C + always @(posedge clk) + in_chain_1 <= in_chain_0; + + // Map in/out + assign a_0 = { 5'd0, in_data_0, { (25-D_WIDTH){1'b0} } }; + assign b_0 = { { (18-S_WIDTH){1'b0} }, in_scale_0 }; + assign c_1 = { { (48-S-D_WIDTH){in_chain_1[D_WIDTH-1]} }, in_chain_1, { (S){1'b0} } }; + + assign out_3 = pout_3[S+:D_WIDTH]; + + // DSP + DSP48E1 #( + .A_INPUT("DIRECT"), + .B_INPUT("DIRECT"), + .USE_DPORT("FALSE"), + .USE_MULT("MULTIPLY"), + .AUTORESET_PATDET("NO_RESET"), + .MASK(48'h3fffffffffff), + .PATTERN(48'h000000000000), + .SEL_MASK("MASK"), + .SEL_PATTERN("PATTERN"), + .USE_PATTERN_DETECT("PATDET"), + .ACASCREG(1), + .ADREG(1), + .ALUMODEREG(1), + .AREG(1), + .BCASCREG(1), + .BREG(1), + .CARRYINREG(1), + .CARRYINSELREG(1), + .CREG(1), + .DREG(1), + .INMODEREG(1), + .MREG(1), + .OPMODEREG(1), + .PREG(1), + .USE_SIMD("ONE48") + ) dsp_I ( + .P(pout_3), + .ACIN(30'h0), + .BCIN(18'h0), + .CARRYCASCIN(1'h0), + .MULTSIGNIN(1'h0), + .PCIN(48'h000000000000), + .ALUMODE(4'b0000), // Z + X + Y + CIN + .CARRYINSEL(3'h0), + .CEINMODE(1'b1), + .CLK(clk), + .INMODE(5'b00000), // B=B2, A=A2 + .OPMODE(7'b0110101), // X=M1, Y=M2, Z=C + .RSTINMODE(rst), + .A(a_0), + .B(b_0), + .C(c_1), + .CARRYIN(1'b0), + .D(25'd0), + .CEA1(1'b0), + .CEA2(1'b1), + .CEAD(1'b1), + .CEALUMODE(1'b1), + .CEB1(1'b0), + .CEB2(1'b1), + .CEC(1'b1), + .CECARRYIN(1'b1), + .CECTRL(1'b1), + .CED(1'b1), + .CEM(1'b1), + .CEP(1'b1), + .RSTA(rst), + .RSTALLCARRYIN(rst), + .RSTALUMODE(rst), + .RSTB(rst), + .RSTC(rst), + .RSTCTRL(rst), + .RSTD(rst), + .RSTM(rst), + .RSTP(rst) + ); + +endmodule // sig_combine diff --git a/gw/sig_delay.v b/gw/sig_delay.v new file mode 100644 index 0000000..9afeaa3 --- /dev/null +++ b/gw/sig_delay.v @@ -0,0 +1,121 @@ +/* + * sig_delay.c + * + * Signal delay line - runtime configurable length + * + * Copyright (C) 2018 sysmocom - systems for mobile communications GmbH + * + * vim: ts=4 sw=4 + */ + +`ifdef SIM +`default_nettype none +`endif + +module sig_delay #( + parameter integer WIDTH = 12 +)( + input wire data_valid, + input wire [WIDTH-1:0] data_in, + output wire [WIDTH-1:0] data_out, + input wire [14:0] delay, + input wire clk, + input wire rst +); + + // Signals + // ------- + + reg [14:0] wr_addr; + reg [14:0] rd_addr; + wire ce; + + + // Control + // ------- + + assign ce = data_valid; + + always @(posedge clk) + begin + if (rst) begin + wr_addr <= 0; + rd_addr <= 0; + end else if (ce) begin + wr_addr <= wr_addr + 1; + rd_addr <= wr_addr - delay; + end + end + + + // Storage + // ------- + + genvar i; + + generate + for (i=0; i