mirror of https://gerrit.osmocom.org/libusrp
138 lines
5.2 KiB
Plaintext
138 lines
5.2 KiB
Plaintext
Matt,
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Here's my idea on the interface to the traffic cop. Basically I'm
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thinking about treating it as 4 separate DMA channels, one for each of
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the four possible "flows". In the interest of simplicity, I think we can
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assign buffers 0,1 to channel 0; 2,3 to channel 1, etc...
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port assignments
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-----------------
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0 SERDES
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1 DSP pipeline
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2 Gigabit ethernet MAC
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3 RAM
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registers
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---------
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MBZ == Must Be Zero
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3 2 1
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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TC_DMA_SRC_{0,3} [WR] ("traffic cop DMA source, channel N")
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(The {0,3} notation means there are four of these registers,
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one for each channel, named TC_DMA_SRC_0, TC_DMA_SRC_1,
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TC_DMA_SRC_2, TC_DMA_3.)
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Specifies where the writing port adapter writes info the buffer, and
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the maximum number of lines to write.
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5 9 9 9
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|0| src | start | end (max) | step |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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src: source port number. E.g., 2 = ethernet MAC (the buffer writer)
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start: starting line number for transfer (32-bit lines)
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end: index of last line to write. I.e., start = 0, end = 0, xfers 1 line.
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step: normally 1.
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TC_DMA_DST_{0,3} [WR]
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Specifies the range of lines that the reading port adapter accesses.
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The number of lines to be transferred is controlled by the source.
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5 9 9 9
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|0| dst | start | end (max) | step |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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dst: destination port number. E.g., 1 = DSP pipeline (the buffer reader)
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start: starting line number tranfer (32-bit lines)
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end: Must be zero, unless a TC_DMA_CMD_SEND_0 or TC_DMA_CMD_SEND_1
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cmd is written to TC_DMA_CTRL_{0,3} in which case this
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specifies the index of the last line to send to the destination.
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step: normally 1.
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TC_DMA_CTRL_{0,3} [WR]
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27 1 4
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| MBZ |A| cmd |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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A: Set if "Host Approval" is required before beginning xfer to dst.
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Used to allow processor to inspect packet for s/w dispatch. If set,
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traffic cop sets PENDING_APPROVAL bit (and causes interrupt?) after the
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2nd line has been written into the buffer. Reader is held off
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until hosts APPROVES or DROPS the buffer.
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cmd: command
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TC_DMA_CMD_RESET 0 // abort active tranfers now; reset to idle state
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TC_DMA_CMD_START 1 // begin transfers according
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TC_DMA_CMD_STOP 2 // stop transfers at completion of current buffer
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TC_DMA_CMD_APPROVE_0 3 // host approves xfer on even buffer, continue
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TC_DMA_CMD_APPROVE_1 4 // host approves xfer on odd buffer, continue
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TC_DMA_CMD_DROP_0 5 // host naks xfer on even buffer, drop buffer and continue
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TC_DMA_CMD_DROP_1 6 // host naks xfer on even buffer, drop buffer and continue
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TC_DMA_CMD_SEND_0 7 // copy buffer 0 to destination (processor init'd buffer)
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TC_DMA_CMD_SEND_1 8 // copy buffer 1 to destination (processor init'd buffer)
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TC_DMA_STATUS_{0,3} [RD]
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10 10
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| nwritten even | nwritten odd | state? | flags |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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nwritten even: number of lines written into even buffer
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nwritten odd: number of lines written into odd buffer
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flag bits:
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bmTCDS_PENDING_APPROVAL_0 (1 << 0) // pending host approval on even buffer
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bmTCDS_PENDING_APPROVAL_1 (1 << 1) // pending host approval on odd buffer
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bmTCDS_WRITE_DONE_0 (1 << 2) // the even buffer write is complete
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bmTCDS_WRITE_DONE_1 (1 << 3) // the odd buffer write is complete
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I think the combination of the "host approval" and WRITE_DONE bits
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will allow us to handle the cases where the host looks and doesn't
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care, and the case where the host looks, cares, and needs to wait
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until it sees the whole packet.
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WRITE_DONE_* should be cleared when the corresponding buffer is
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selected to be written into (e.g., when swapping buffers, and at init)
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prior to writing the first line. WRITE_DONE_* is set when the
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requested number of lines have been written into the buffer.
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I also want a "global status register" that pulls the N flag bits
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from each of the 4 status registers into a single word. This should
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allow me to read a single word to figure out what to do.
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TC_DMA_STATUS_GLOBAL [RD]
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| flags3 | flags2 | flags1 | flags0 |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// some kind of registers to enable and ack interrupts
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TC_DMA_INTR_EN [WR] // enable particular interrupts
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TC_DMA_INTR_CLR [WR] // clear particular pending interrupts
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