mirror of https://gerrit.osmocom.org/libusrp
24 lines
464 B
Verilog
24 lines
464 B
Verilog
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module setting_reg
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( input clock, input reset, input strobe, input wire [6:0] addr,
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input wire [31:0] in, output reg [31:0] out, output reg changed);
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parameter my_addr = 0;
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always @(posedge clock)
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if(reset)
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begin
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out <= #1 32'd0;
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changed <= #1 1'b0;
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end
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else
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if(strobe & (my_addr==addr))
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begin
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out <= #1 in;
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changed <= #1 1'b1;
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end
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else
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changed <= #1 1'b0;
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endmodule // setting_reg
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